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Multiple choice question for engineering

Set 1

1. Which of the following is an analogue extension of the VHDL?
a) VHDL-AMS
b) System VHDL
c) Verilog
d) System Verilog

View Answer

Answer: a [Reason:] The VHDL-AMS is the extension of the VHDL and this includes the analogue and mixed behaviour of the signals.

2. Which of the following support the modelling partial differentiation equation?
a) gate level
b) algorithmic level
c) system level
d) switch level

View Answer

Answer: c [Reason:] There are a variety of levels for designing the embedded systems and each level has its own language. The system level is one such kind which has many peculiarities with respect to the other levels. The system model denotes the entire embedded system and includes the mechanical as well as the information processing aspects. This also supports the modelling of the partial differential equations, which is a key requirement in the modelling.

3. Which level simulates the algorithms that are used within the embedded systems?
a) gate level
b) circuit level
c) switch level
d) algorithmic level

View Answer

Answer: d [Reason:] The algorithmic level simulates the algorithm which is used within in the embedded system.

4. Which level model components like ALU, memories registers, muxes and decoders?
a) switch level
b) register-transfer level
c) gate level
d) circuit level

View Answer

Answer: b [Reason:] The register-transfer level modelling models all the components like the arithmetic and logical unit(ALU), memories, registers, muxes, decoders etc and this modelling is always cycled truly.

5. Which of the following is the most frequently used circuit-level model?
a) SPICE
b) VHDL
c) Verilog
d) System Verilog

View Answer

Answer: a [Reason:] The SPICE is simulation program with integrated circuit emphasis, which is a frequently used circuit-level in the early days. It is used to find the behavior and the integrity of the circuit.

6. Which model includes the geometric information?
a) switch-level model
b) layout model
c) gate level model
d) register-transfer level

View Answer

Answer: b [Reason:] The layout reflects the actual circuit model. It includes the geometric information and cannot be simulated directly since it does not provide the information regarding the behavior.

7. Which model cannot simulate directly?
a) circuit level model
b) switch-level model
c) gate level model
d) layout model

View Answer

Answer: d [Reason:] The layout model reflects the actual circuit model and this include the geometric information and this model cannot be simulated directly because it does not provide the information regarding the behavior.

8. Which of the following models the components like resistors, capacitors etc?
a) register-transfer level
b) layout model
c) circuit level model
d) switch-level model

View Answer

Answer: c [Reason:] The circuit-level model simulation is used for the circuit theory and its components such as the resistors, inductors, capacitors, voltage sources, current sources. This simulation also involves the partial differential equations.

9. Which model uses transistors as their basic components?
a) switch model
b) gate level
c) circuit level
d) layout model

View Answer

Answer: a [Reason:] The switch model can be used in the simulation of the transistors since the transistor is the very basic component in a switch. It is capable of reflecting bidirectional transferring of the information.

10. Which model is used to denote the boolean functions?
a) switch level
b) gate level model
c) circuit level
d) layout model

View Answer

Answer: b [Reason:] The gate level model is used to denote the boolean functions and the simulation only consider the behaviour of the gate.

11. Which model is used for the power estimation?
a) gate-level model
b) layout model
c) circuit model
d) switch model

View Answer

Answer: a [Reason:] The gate level model is used to denote the boolean functions and the simulation only consider the behaviour of the gate. This model is also useful in the power estimation since it provides the accurate information about the signal transition probabilities.

12. In which model, the effect of instruction is simulated and their timing is not considered?
a) gate-level model
b) circuit model
c) coarse-grained model
d) layout model

View Answer

Answer: c [Reason:] The coarse-grained model is a kind of the instruction set level modelling in which only the effect of instruction is simulated and the timing is not considered. The information which is provided in the manual is sufficient for this type of modelling.

13. Which models communicates between the components?
a) transaction level modelling
b) fine-grained modelling
c) coarse-grained modelling
d) circuit level model

View Answer

Answer: a [Reason:] The transaction level modelling is a type of instruction set level model. This modelling helps in the modelling of components which is used for the communication purpose. It also models the transaction, such as read and writes cycles.

14. Which of the following has a cycle-true set of simulation?
a) switch-level model
b) layout model
c) circuit-level
d) fine-grained model

View Answer

Answer: d [Reason:] The fine-grained model has the cycle-true instruction set simulation. In this modelling, it is possible to compute the exact number of clock cycles which is required to run an application.

Set 2

1. What do COOL stand for?
a) coprocessor tool
b) codesign tool
c) code tool
d) code control

View Answer

Answer: b [Reason:] The COOL is the codesign tool which is one of the optimisation technique for partitioning the software and the hardware.

2. How many inputs part does COOL have?
a) 2
b) 4
c) 5
d) 3

View Answer

Answer: d [Reason:] The codesign tool consists of three input parts. These are target technology, design constraints and the behaviour and each input follows different functions. The target technology comprises the information about the different hardware platform components available within the system, design constraints are the second part of the input which contains the design constraints, and the behaviour part is the third input which describes the required overall behaviour.

3. Which part of the COOL input comprises information about the available hardware platform components?
a) target technology
b) design constraints
c) both behaviour and design constraints
d) behaviour

View Answer

Answer: a [Reason:] The codesign tool consists of three input parts which are described as target technology, design constraints and the behavior. Each input does different functions. The target technology comprises the information about the different hardware platform components available within the system.

4. What does the second part of the COOL input comprise?
a) behaviour and target technology
b) design constraints
c) behaviour
d) target technology

View Answer

Answer: b [Reason:] The second part of the COOL input comprises of the design constraints such as the latency, maximum memory size, required throughput or maximum area for application-specific hardware.

5. What do the third part of the COOL input comprise?
a) design constraints and target technology
b) design constraints
c) behaviour
d) target technology

View Answer

Answer: c [Reason:] The codesign tool consists of three input parts and the third part of the COOL input describes the overall behaviour of the system. The hierarchical task graphs are used for this.

6. How many edges does the COOL use?
a) 1
b) 2
c) 3
d) 4

View Answer

Answer: b [Reason:] The codesign tool has 2 edges. These are timing edges and the communication edges. The timing edge provides the timing constraints whereas the communication edge contains the information about the amount of information to be exchanged.

7. Which edge provides the timing constraints?
a) timing edge
b) communication edge
c) timing edge and communication edge
d) special edge

View Answer

Answer: a [Reason:] The codesign tool has 2 edges. They are timing edges and the communication edges. The timing edge provides the timing constraints.

8. Which edge of the COOL contains information about the amount of information to be exchanged?
a) regular edge
b) timing edge
c) communication edge
d) special edge

View Answer

Answer: c [Reason:] The codesign tool has 2 edges and these are timing edges and the communication edges. The communication edge contains the information about the amount of information to be exchanged.

9. What does Index set KH denotes?
a) processor
b) hardware components
c) task graph nodes
d) task graph node type

View Answer

Answer: b [Reason:] There is certain index set which is used in the IP or the integer programming model. The KH denotes the hardware component types.

10. What do Index set L denotes?
a) processor
b) task graph node
c) task graph node type
d) hardware components

View Answer

Answer: c [Reason:] The index set is used in the IP or the integer programming model. The Index set KP denotes the processor, I denote the task graph nodes and the L denotes the task graph node type.

Set 3

1. What do FRIDGE stand for?
a) fixed-point programming design environment
b) floating-point programming design environment
c) fixed-point programming decoding
d) floating-point programming decoding

View Answer

Answer: a [Reason:] Certain tools are available which are developed for the optimization programmes and one such tool is the FRIDGE or fixed-point programming design environment, commercially made by Synopsys System Studio.

2. Which of the following tool can replace the floating point arithmetic to fixed point arithmetic?
a) SDS
b) FAT
c) VFAT
d) FRIDGE

View Answer

Answer: d [Reason:] There are certain tools available which are developed for the optimization programmes and one such tool is the FRIDGE or fixed-point programming design environment, commercially made available by Synopsys System Studio. This tool can is used in the transformation program, that is the conversion of floating point arithmetic to the fixed point arithmetic. This is widely used in the signal processing.

3. Which programming algorithm is used in the starting process of the FRIDGE?
a) C++
b) JAVA
c) C
d) BASIC

View Answer

Answer: c [Reason:] The FRIDGE tool uses C programming algorithm in the initial stage and is converted to a fixed-C algorithm which extends C by two extends.

4. In which loop transformation, a single loop is split into two?
a) loop tiling
b) loop fusion
c) loop permutation
d) loop unrolling

View Answer

Answer: b [Reason:] Many loop transformation are done for the optimization of the program and one such loop transformation is the loop fusion in which a single loop is split and the loop fission includes the merging of the two separate loops.

5. Which loop transformations have several instances of the loop body?
a) loop fusion
b) loop unrolling
c) loop fission
d) loop tiling

View Answer

Answer: b [Reason:] The loop unrolling is a standard transformation which creates several instances of the loop body and the number of copies of the loop is known as the unrolling factor.

6. The number of copies of loop is called as
a) rolling factor
b) loop factor
c) unrolling factor
d) loop size

View Answer

Answer: c [Reason:] The number of copies of the loop is known as the unrolling factor and it is a standard transformation that produces instances of the loop body.

7. Which of the following can reduce the loop overhead and thus increase the speed?
a) loop unrolling
b) loop tiling
c) loop permutation
d) loop fusion

View Answer

Answer: a [Reason:] The loop unrolling can reduce the loop overhead, that is the fewer branches per execution of the loop body, which in turn increases the speed but is only restricted to loops with a constant number of iteration. The unrolling can increase the code size.

8. Which loop transformation can increase the code size?
a) loop permutation
b) loop fusion
c) loop fission
d) loop unrolling

View Answer

Answer: d [Reason:] The loop unrolling can decrease the loop overhead, the fewer branches per execution of the loop body and this can increase the speed but is only restricted to loops with a constant number of iteration and thus the loop unrolling can increase the code size.

9. Which memories are faster in nature?
a) RAM
b) ROM
c) Scratch pad memories
d) EEPROM

View Answer

Answer: c [Reason:] As the memory size decreases, it is faster in operation, that is the smaller memories are faster than the larger memories. The small memories are caches and the scratch pad memories.

10. Which loop transformation reduces the energy consumption of the memory systems?
a) loop permutation
b) loop tiling
c) loop fission
d) loop fusion

View Answer

Answer: b [Reason:] The loop tiling can reduce the energy the consumption of the memory systems.

Set 4

1. Which of the following allows the reuse of the software and the hardware components?
a) platform based design
b) memory design
c) peripheral design
d) input design

View Answer

Answer: a [Reason:] The platform design allows the reuse of the software and the hardware components in order to cope with the increasing complexity in the design of embedded systems.

2. Which of the following is the design in which both the hardware and software are considered during the design?
a) platform based design
b) memory based design
c) software/hardware codesign
d) peripheral design

View Answer

Answer: c [Reason:] The software/hardware codesign is the one which having both hardware and software design concerns. This will help in the right combination of the hardware and the software for the efficient product.

3. What does API stand for?
a) address programming interface
b) application programming interface
c) accessing peripheral through interface
d) address programming interface

View Answer

Answer: b [Reason:] The platform-based design helps in the reuse of both the hardware and the software components. The application programming interface helps in extending the platform towards the software applications.

4. Which activity is concerned with identifying the task at the final embedded systems?
a) high-level transformation
b) compilation
c) scheduling
d) task-level concurrency management

View Answer

Answer: d [Reason:] There are many design activities associated with the platforms in the embedded system and one such is the task-level concurrency management which helps in identifying the task that needed to be present in the final embedded systems.

5. In which design activity, the loops are interchangeable?
a) compilation
b) scheduling
c) high-level transformation
d) hardware/software partitioning

View Answer

Answer: c [Reason:] The high-level transformation are responsible for the high optimizing transformations, that is, the loops can be interchanged so that the accesses to array components become more local.

6. Which design activity helps in the transformation of the floating point arithmetic to a fixed point arithmetic?
a) high-level transformation
b) scheduling
c) compilation
d) task-level concurrency management

View Answer

Answer: a [Reason:] The high-level transformation are responsible for the high optimizing transformations, that is, for the loop interchanging and the transformation of the floating point arithmetic to the fixed point arithmetic can be done by the high-level transformation.

7. Which design activity is in charge of mapping operations to hardware?
a) scheduling
b) high-level transformation
c) hardware/software partitioning
d) compilation

View Answer

Answer: c [Reason:] The hardware/software partitioning is the activity which is in charge of mapping operations to the software or to the hardware.

8. Which of the following is approximated during hardware/software partitioning, during task-level concurrency management?
a) scheduling
b) compilation
c) task-level concurrency management
d) high-level transformation

View Answer

Answer: a [Reason:] The scheduling is performed in several contexts. It should be approximated with the other design activities like the compilation, hardware/software partitioning, and task-level concurrency management. The scheduling should be precise for the final code.

9. Which of the following is a process of analyzing the set of possible designs?
a) design space exploration
b) scheduling
c) compilation
d) hardware/software partitioning

View Answer

Answer: a [Reason:] The design space exploration is the process of analyzing the set of designs and the design which meet the specification is selected.

10. Which of the following is a meet-in-the-middle approach?
a) peripheral based design
b) platform based design
c) memory based design
d) processor design

View Answer

Answer: b [Reason:] The platform is an abstraction layer which covers many possible refinements to a lower level and is mainly follows a meet-in-the-middle approach.

Set 5

1. How many kinds of wait statements are available in the VHDL design?
a) 3
b) 4
c) 5
d) 6

View Answer

Answer: b [Reason:] There are four kinds of wait statements. These are wait on, wait for, wait until and wait.

2. Which wait statement does follow a condition?
a) wait for
b) wait until
c) wait
d) wait on

View Answer

Answer: b [Reason:] The wait until follows a condition. The condition may be an arithmetic or logical one and the wait for statement follows time duration, it might be in microseconds or nanoseconds or any other time unit. Similarly, the wait on statement follows a signal list and the wait statement suspends indefinitely.

3. Which wait statement does follow duration?
a) wait for
b) wait
c) wait until
d) wait on

View Answer

Answer: a [Reason:] The wait for statement follows time duration, it might be in microseconds or nanoseconds or any other time unit.

4. Which of the following is a C++ class library?
a) C++
b) C
c) JAVA
d) SystemC

View Answer

Answer: d [Reason:] System C is a C++ class library which helps in solving the behavioural, resolution, simulation time problems.

5. Which model of SystemC uses floating point numbers to denote time?
a) SystemC 1.0
b) SystemC 2.0
c) SystemC 3.0
d) SystemC 4.0

View Answer

Answer: a [Reason:] The SystemC includes several models of the time units. SystemC 1.0 uses floating point numbers which denote time.

6. Which model of SystemC uses the integer number to define time?
a) SystemC 1.0
b) SystemC 2.0
c) SystemC 3.0
d) SystemC 4.0

View Answer

Answer: b [Reason:] The SystemC includes several models of the time. System 2.0 is an integer model to define time and this model also supports physical units such as microseconds, nanoseconds, picoseconds etc.

7. Which model of the SystemC helps in the communication purpose?
a) SystemC 2.0
b) SystemC 3.0
c) SystemC 1.0
d) SystemC 4.0

View Answer

Answer: a [Reason:] The SystemC 2.0 provides the channel port, and interface ports for the communication purpose.

8. Which C++ class is similar to the hardware description language like VHDL?
a) SystemC
b) Verilog
c) C
d) JAVA

View Answer

Answer: a [Reason:] The SystemC is a C++ class which is similar to the hardware description languages like VHDL and Verilog. The execution and simulation time in the SystemC is almost similar to the VHDL.

9. What do ESL stand for?
a) EEPROM system level
b) Electronic-system level
c) Electrical system level
d) Electron system level

View Answer

Answer: b [Reason:] The ESL is electronic-system level and the SystemC is associated with the ESL and TLM. The SystemC is also applied to the architectural exploration, performance modelling, software development and so on.

10. What to TLM stand for?
a) transfer level modelling
b) triode level modelling
c) transaction level modelling
d) transistor level modelling

View Answer

Answer: c [Reason:] The TLM is transaction-level modelling and the SystemC is associated with the ESL and TLM.