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Multiple choice question for engineering

Set 1

1. Which task swapping method does not require the time critical operations?
a) time slice
b) pre-emption
c) cooperative multitasking
d) schedule algorithm

View Answer

Answer: a [Reason:] Time-critical operations are not essential in the time slice mechanism. Time slice mechanism describes the task switching in a particular time slot.

2. Which task swap method works in a regular periodic point?
a) pre-emption
b) time slice
c) schedule algorithm
d) cooperative multitasking

View Answer

Answer: b [Reason:] The time slicing works by switching task in regular periodic points in time, that is, any task that needs to run next will have to wait until the current time slice is completed.

3. Which of the following determines the next task in the time slice method of task swapping?
a) scheduling program
b) scheduling application
c) scheduling algorithm
d) scheduling task

View Answer

Answer: c [Reason:] The time slice mechanism can also be used a scheduling method in which the task to run next is determined by the scheduling algorithm.

4. Which of the following can be used to distribute the time slice across all the task?
a) timer
b) counter
c) round-robin
d) task slicing

View Answer

Answer: c [Reason:] The time slice based system uses fairness scheduler or round robin to distribute the time slices across all the tasks that need to run in a particular time slot.

5. What do a time slice period plus a context switch time of the processor determines?
a) scheduling task
b) scheduling algorithm
c) context task
d) context switch time

View Answer

Answer: d [Reason:] The context switch time of the processor along with the time slice period determines the context switch time of the system which is an important factor in a system response, that is, the time period can be reduced to improve the context switching of the system which will increase the number of task switches.

6. Which can increase the number of task switches?
a) time period
b) frequency
c) time rate
d) number of cycles

View Answer

Answer: a [Reason:] The time period can be reduced to improve the context switching of the system which will increase the number of task switches.

7. Which mechanism is used behind the Windows 3.1?
a) time slice
b) pre-emption
c) cooperative multitasking
d) scheduling algorithm

View Answer

Answer: c [Reason:] The cooperative multitasking mechanism is used the Windows 3.1 but it is not applicable to the real-time operating systems.

8. Which of the following provides an illusion of multitasking?
a) single task operating system
b) multitasking operating system
c) cooperative multitasking
d) pre-emption

View Answer

Answer: c [Reason:] The cooperative multitasking co-operates between them which provides the illusion of multitasking. This is done by periodically executing the tasks.

9. Which task method follows a currently running task to be stopped by a higher priority task?
a) scheduling algorithm
b) time slice
c) cooperative multitasking
d) pre-emption

View Answer

Answer: d [Reason:] The pre-emption is an alternative method of the time slice where the currently running task can be stopped or preempted or switched out by a higher priority active task.

10. Which of the following requires programming within the application?
a) time slice
b) scheduling algorithm
c) pre-emption
d) cooperative multitasking

View Answer

Answer: d [Reason:] The cooperative multitasking requires programming within the application and the system can be destroyed by a single program which hogs all the processing power. Therefore, it is not applicable in the real-time operating system.

11. What does RMS stand for?
a) rate monotonic scheduling
b) rate machine scheduling
c) rate monotonic software
d) rate machine software

View Answer

Answer: a [Reason:] The rate monotonic scheduling is a method that is used to assign priority for a pre-emptive system such that the correct execution can be guaranteed.

12. Which of the following task swapping method is a better choice in the embedded systems design?
a) RMS
b) pre-emptive
c) cooperative multitasking
d) time slice

View Answer

Answer: b [Reason:] The pre-emptive method of task swapping is the first choice for embedded system design because of its better system response.

Set 2

1. Which of the following can be used to refer to entities within the RTOS?
a) threads
b) kernels
c) system
d) applications

View Answer

Answer: a [Reason:] The threads and processes can be used to refer to entities within the RTOS. They provide an interchangeable replacement for the task. They have a slight difference in their function. A process is a program in execution and it has its own address space whereas threads have a shared address space. The task can be defined as a set of instructions which can be loaded into the memory.

2. Which of the following defines the set of instructions loaded into the memory?
a) process
b) task
c) thread
d) system hardware

View Answer

Answer: b [Reason:] The task can be defined by the set of instructions which is loaded into the memory and it can split into two or more tasks.

3. Which of the following uses its own address space?
a) thread
b) process
c) task
d) kernel

View Answer

Answer: a [Reason:] Threads uses a shared memory space and it uses the memory space of the process.

4. Which of the following does not uses a shared memory?
a) process
b) thread
c) task
d) kernel

View Answer

Answer: a [Reason:] The program in execution is known as the process. The process does not share the memory space but the threads have a shared memory address. When the CPU switches from process to another, the current information is stored in the process descriptor.

5. Which of the following can own and control the resources ?
a) thread
b) task
c) system
d) peripheral

View Answer

Answer: b [Reason:] The task and process have several characteristics and one such is that the task or process can own or control resources and it has threads of execution which are the paths through the code.

6. Which can be supported if the task or process maintains a separate data area for each thread?
a) single thread system
b) mono thread system
c) multiple threads
d) dual threads

View Answer

Answer: c [Reason:] The multiple threads can be supported only if the process or task can maintain a separate data areas for each thread.

7. Which of the following possesses threads of execution?
a) process
b) thread
c) kernel
d) operating system

View Answer

Answer: a [Reason:] The process has threads of execution which are the paths through the code.

8. Which of the following is inherited from the parent task?
a) task
b) process
c) thread
d) kernel

View Answer

Answer: c [Reason:] The threads are a part of the process, that is, it uses a shared memory of the process and therefore said that its resources are inherited from the parent process or task.

9. Which term is used to encompass more than a simple context switch?
a) process
b) single thread system
c) thread
d) multithread

View Answer

Answer: a [Reason:] The process includes the additional information which is used to encompass more than a simple context switch. This is similar to the task switching, that is why it is said that process and task are interchangeable.

10. Which can be considered as the lower level in the multitasking operating system?
a) process
b) task
c) threads
d) multi threads

View Answer

Answer: c [Reason:] In the multitasking operating system, the process and tasks form the higher level whereas the thread is the lower level. But in a simple operating system, there is no difference between the context switch of thread and the process.

Set 3

1. Which of the following can be done to ensure that all interrupts are recognised?
a) reset pin
b) external ready pin
c) handshaking
d) acknowledgement

View Answer

Answer: c [Reason:] The exception handler performs some kind of handshaking to ensure that all the interrupts are recognised.

2. How many types of exceptions are associated with the asynchronous imprecise?
a) 1
b) 2
c) 3
d) 4

View Answer

Answer: b [Reason:] Two types of exceptions are associated with the asynchronous imprecise. These are system reset and machine checks.

3. How is the internal registers and memories are reset?
a) system reset
b) memory reset
c) peripheral reset
d) software reset

View Answer

Answer: a [Reason:] By doing the system reset, all the current processing are stopped and the internal registers and the memories are reset.

4. How is the machine check exception is taken in an asynchronous imprecise?
a) ME bit
b) EE bit
c) FE0
d) FE1

View Answer

Answer: a [Reason:] The machine check exception is taken only if the ME bit of the MSR is set. If it is cleared, the processor will enter into a check stop state.

5. Which of the following are the exceptions associated with the asynchronous imprecise?
a) decrementer interrupt
b) machine check
c) instruction dependent
d) external interrupt

View Answer

Answer: b [Reason:] The machine check and the system reset are two types of exceptions which are associated with the asynchronous imprecise.

6. Which of the following possesses an additional priority?
a) asynchronous precise
b) asynchronous imprecise
c) synchronous precise
d) synchronous imprecise

View Answer

Answer: c [Reason:] The synchronous precise exceptions provide additional priority because it is possible for an instruction to generate more than one exception.

7. Which of the following has more priority?
a) system reset
b) machine check
c) external interrupt
d) decrementer interrupt

View Answer

Answer: a [Reason:] The system reset has the first priority then comes the machine reset, next priority moves for the instruction dependent, and the next priority is external interrupt, and last priority level goes for the decrementer interrupt.

8. Which bit controls the external interrupts and the decrementer exceptions?
a) FE1
b) FE0
c) EE
d) ME

View Answer

Answer: c [Reason:] The EE bit in the MSR controls the external interrupts and the decrementer exceptions.

9. Which bit controls the machine check exceptions?
a) ME
b) FE0
c) FE1
d) EE

View Answer

Answer: a [Reason:] The ME bit in the MSR controls the machine check interrupts.

10. Which bits control the floating point exceptions?
a) EE
b) FE0
c) FE1
d) both FE1 and FE2

View Answer

Answer: d [Reason:] The FE0 and FE1 controls the floating point exceptions.

11. Which of the following is an 16 kbyte block?
a) register
b) vector table
c) buffer
d) lookaside buffer

View Answer

Answer: b [Reason:] The vector table is an 16 kbyte block which is divided into 256 byte divisions in which each division is allocates for a particular exceptions and it also contains the handler routine associated with the exceptions.

Set 4

1. Which of the following helps in the generation of waveforms?
a) timer
b) inputs
c) outputs
d) memory

View Answer

Answer: a [Reason:] The embedded systems have a timing component called timer or counter which helps in the timing reference for control sequence, provides system tick for the operating system and also helps in the generation of waveforms for the serial port baud rate generation.

2. Which bit size determines the slowest frequency?
a) counter size
b) pre-scalar value
c) counter
d) timer

View Answer

Answer: b [Reason:] The pre-scalar value determines the slowest frequency that can be generated from a given clock input. Actually the bit size are determined by the pre-scalar value and the conuter size.

3. Which bit size determines the maximum value of the counter-derived period?
a) counter size
b) pre-scalar value
c) bit size
d) byte size

View Answer

Answer: a [Reason:] The bit size are basically determined by its fundamental properties, that is, the pre-scalar value and the counter size. The counter size determines the maximum value of the counter derived period.

4. Which of the following timer is suitable for IBM PC?
a) IA-32
b) Intel 8253
c) Intel 64
d) 8051 timer

View Answer

Answer: b [Reason:] The Intel 8253 timer is suitable for the IBM PC. IA-32 and Intel 64 are the offload timers used only for Intel. The 8051 timer is used for the timing program in 8051.

5. Which of the following is mode 0 in 8253?
a) interrupt on start count
b) interrupt for wait statement
c) interrupt on terminal count
d) no interrupt

View Answer

Answer: c [Reason:] The interrupt on the terminal count is known as mode 0 for the 8253. An initial value is loaded into the count register and then starts to count down at the frequency which is determined by the clock input. When the count reaches zero, an interrupt is generated.

6. Which determines the mode 1 in the Intel 8253?
a) interrupt on terminal count
b) programmable one-shot
c) rate generator
d) square wave rate generator

View Answer

Answer: b [Reason:] Programmable one-shot is also known as mode 1 in the Intel 8253. In mode 1, a single pulse with a programmable duration is created first and then the pulse length is loaded into the counter and when the external gate signal is high, the rising edge starts the counter to count down to zero and the counter output signal goes high to start the external pulse. When the counter reaches to zero, the counter output goes low and thus the ending of the pulse.

7. Which mode of 8253 can provide pulse width modulation?
a) programmable one-shot
b) square wave rate generator
c) software triggered strobe
d) hardware triggered strobe

View Answer

Answer: a [Reason:] Mode 1 of the Intel 8253 can provide pulse width modulation for the power control where the gate is connected to a zero crossing detector or a clock source.

8. Which of the following is the mode 3 in the Intel timer 8253?
a) rate generator
b) hardware triggered strobe
c) square wave rate generator
d) software triggered strobe

View Answer

Answer: a [Reason:] The rate generator is the mode 3 in Intel 8253 timer. The square wave generator is the mode 4 and the hardware triggered strobe is the mode 5 in the Intel 8253 timer.

9. Which of the following determines the rate generation?
a) divide by N
b) multiply by N
c) addition by N
d) subtraction by N

View Answer

Answer: a [Reason:] The rate generator mode is determined by the mode 3 with the Intel 8253. It is a simple divide by N mode where N is the initial value loaded into the counter.

10. Which mode of the Intel 8253 timer can generate a square wave?
a) mode 1
b) mode 2
c) mode 3
d) mode 4

View Answer

Answer: d [Reason:] The mode 4 is the square wave generator. This mode is similar to the mode 3 except that the waveform is a square wave.

Set 5

1. What shows the brightness of the pixel in a digital signal processor?
a) luminance
b) transparent
c) chrominance
d) opaque

View Answer

Answer: a [Reason:] The color image of a digital signal processor have multiple channels. The brightness of the pixel is determined by luminance and the color of the pixel is determined by chrominance.

2. What is the color format of chrominance in a digital signal processor?
a) VGBA
b) VIBGYOR
c) White
d) RGBA

View Answer

Answer: d [Reason:] RGBA colors has four channels red, green, blue, and alpha, which is transparent.

3. Which of the following processor are designed to perform calculations in graphics rendering?
a) GPU
b) digital signal processor
c) microprocessor
d) microcontroller

View Answer

Answer: a [Reason:] Graphics processing unit is designed to perform calculations in graphics rendering. Intel, NVIDIA, and AMD are dominant providers of GPU.

4. Which of the processor is a good match for applications such as video games?
a) GPU
b) VLIW
c) Coprocessor
d) Microcontroller

View Answer

Answer: a [Reason:] GPU is a graphics processing unit. Therefore, more graphical images can be created by GPU which is necessary for video games. Therefore, GPU is a good match for video games.

5. Which of the following statement is true for concurrency?
a) different parts of the program executes physically
b) different parts of the program executes sequentially
c) different parts of the program executes conceptually
d) different parts of the program executes sequentially and physically

View Answer

Answer: c [Reason:] A concurrent program executes different parts of the program conceptually, a parallel program executes different programs physically and a non-concurrent program executes the program in a sequential order.

6. Which is an imperative language?
a) C program
b) SQL
c) XQuery
d) Concurrent model of HDL

View Answer

Answer: a [Reason:] Imperative language is one which executes the program in a sequential order. C program is an example of imperative language, SQL and XQuery are examples of declarative languages or non-imperative language. Concurrent model in HDL is a hardware description language which executes the program concurrently.

7. Which of the following instructions supports parallel execution?
a) VLIW
b) TTA
c) ALU operation
d) Test-and-set instructions

View Answer

Answer: a [Reason:] VLIW is a very long instruction word which receives many instructions and is executed in one instructed word. VLIW is majorly designed for instruction-level parallel (ILP) that is, it can execute codes concurrently or parallel in some time. TTA is a transport triggered architecture which is a type of CPU design which programs controlling the internal buses of the processor. Test-and-set is used to write to a memory location and return its old values. ALU used to perform arithmetic and logic operations.

8. Who invented VLIW architecture?
a) Josh Fisher
b) John Ellis
c) John Ruttenberg
d) John O’Donnell

View Answer

Answer: a [Reason:] Josh Fisher from Yale Universities invented the concept of VLIW architecture. John Ellis described the VLIW compiler. John Ruttenberg develops some important algorithms in scheduling.

9. What is ILP?
a) instruction-level parallelism
b) instruction-level panel
c) instruction-language panel
d) inter-language parallelism

View Answer

Answer: a [Reason:] A processor which supports instruction-level parallelism can perform multiple independent operations in every instruction cycle. Basically, there are four types of instructions. These are CISC instructions, subword parallelism, superscalar, and VLIW.

10. Which ILP supports the ALU division?
a) Subword parallelism
b) CISC
c) Superscalar
d) VLIW

View Answer

Answer: a [Reason:] In subword parallelism, the wide ALU is divided into smaller slices which enable simultaneous arithmetic and logical operations.

11. Which is a vector processor?
a) Subword parallelism
b) CISC
c) Superscalar
d) VLIW

View Answer

Answer: a [Reason:] Subword parallelism is a form of a vector processing. A vector processor is the one whose instruction set includes operations on multiple data elements simultaneously.

12. Which of the following architecture supports out-of-order execution?
a) RISC
b) CISC
c) Superscalar
d) Subword parallelism

View Answer

Answer: c [Reason:] Superscalar architecture support out-of-order execution in which the instructions later in the stream are executed before earlier instructions.

13. Which is an example of superscalar architecture?
a) Pentium 4
b) 8086
c) 80386
d) Pentium pro

View Answer

Answer: a [Reason:] Pentium 4 is a single core CPU used in desktops, laptops which are proposed by Intel. It has Netburst architecture.

14. Which of the following is a combination of several processors on a single chip?
a) Multicore architecture
b) RISC architecture
c) CISC architecture
d) Subword parallelism

View Answer

Answer: a [Reason:] The Multicore machine is a combination of many processors on a single chip. The heterogeneous multicore machine also combines a variety of processor types on a single chip.

15. Which is an example of the multi-core processor which possesses 10 cores?
a) Intel Xeon E7-2850
b) AMD Phenom IIX2
c) Intel core duo
d) AMD Phenom IIX3

View Answer

Answer: a [Reason:] Intel Xeon E7-2850 have ten cores whereas AMD Phenom IIx2 and Intel core cuo has two cores and AMD Phenom IIX3 has three cores.