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Multiple choice question for engineering

Set 1

1. Which of the following have a 16 Mbytes addressed range?
a) PowerPC
b) M68000
c) DSP56000
d) TMS 320

View Answer

Answer: b [Reason:] The M68000 family has a 16 Mbyte addressing range. The PowerPC family has a larger 4 Gbyte range and the DSP56000 has a 128-kilo word address space.

2. Which of the following can destroy the accuracy in the algorithms?
a) delays
b) error signal
c) interrupt
d) mmu

View Answer

Answer: a [Reason:] The delays occurring in the memory management unit can destroy the accuracy in the algorithms and in order to avoid this, the linear addressing range should be increased.

3. How many numbers of ways are possible for allocating the memory to the modular blocks?
a) 1
b) 2
c) 3
d) 4

View Answer

Answer: c [Reason:] Most of the systems have a multitasking operating system in which the software consist of modular blocks of codes which run under the control of the operating system. There are three ways for allocating memory to these blocks. The first way distributes the block in a predefined way. The second way for allocating memory includes relocation or position independency in the software and the other way of allocating memory to the block is the address translation in which the logical address is translated to the physical address.

4. Which of the following is replaced with the absolute addressing mode?
a) relative addressing mode
b) protective addressing mode
c) virtual addressing mode
d) temporary addressing mode

View Answer

Answer: a [Reason:] The memory allocation of the modular blocks can be done by the writing the software program in relocatable or position independent manner which can execute anywhere in the memory map, but relocatable code must have the same address between its data and code segments. This is used to avoid the use of absolute addressing modes which is replaced by the relative addressing modes.

5. What is the main purpose of the memory management unit?
a) address translation
b) large storage
c) reduce the size
d) provides address space

View Answer

Answer: a [Reason:] The memory management unit handles with physical addresses. Therefore, the virtual or the logical address is first translated to the physical address.

6. Which of the following provides stability to the multitasking system?
a) memory
b) DRAM
c) SRAM
d) Memory partitioning

View Answer

Answer: d [Reason:] The memory partitioning provides stability to the multitasking system so that the errors within one task will not corrupt the other tasks.

7. Which of the following is used by the M68000 family?
a) M68000
b) 80386
c) 8086
d) 80286

View Answer

Answer: a [Reason:] The M68000 uses memory partitioning by the use of function code or by the combination of superscalar signals and the Harvard architecture.

8. What can be done for the fine grain protection of the processor?
a) add extra description bit
b) add error signal
c) add wait stage
d) remains unchanged

View Answer

Answer: a [Reason:] The finer grain protection of memory management is achieved by the addition of extra description bit to an address to declare its status. The memory management unit can detect an error if the task attempts to access memory that has not been allocated to it or a certain kind of mismatch occurs.

9. Which of the following technique is used by the UNIX operating system?
a) logical address memory
b) physical address memory
c) virtual memory technique
d) translational address

View Answer

Answer: c [Reason:] In the workstation and in the UNIX operating system virtual memory technique is frequently used in which the main memory is divided into different segments and pages. These pages will have a virtual address which can increase the address spacing.

10. Which of the following consist two lines of legs on both sides of a plastic or ceramic body?
a) SIMM
b) DIMM
c) Zig-zag
d) Dual in-line

View Answer

Answer: d [Reason:] The dual-in-line package consists of two lines of legs on both sides of the plastic or ceramic. Most commonly used is BIOS EPROMs, DRAM and SRAM.

11. Which package has high memory speed and change in the supply?
a) DIP
b) SIMM
c) DIMM
d) zig-zag

View Answer

Answer: c [Reason:] DIMM is a special version of SIMM which is 168-bits wider bus and looks similar to a larger SIMM. The wider bus increases the memory speed and change in supply voltage.

12. Which is a subassembly package?
a) dual-in-line
b) zig-zag
c) simm
d) ceramic shell

View Answer

Answer: c [Reason:] The SIMM is basically a subassembly, not a package. It is a small board which possesses finger connection on the bottom and sufficient memory on the board in order to make up the required configuration.

13. What is the required voltage of DIMM?
a) 2V
b) 2.2V
c) 5V
d) 3.3V

View Answer

Answer: d [Reason:] For increasing the speed and reducing the power consumption, it is necessary to reduce the power supply. Today’s CPUs and memories have 3.3V supply or even lower instead of the signal level from 0 to 5V. DIMMS are described by its voltage, speed, and memory type respectively as 3.3V 133MHz SDRAM DIMM.

14. Which memory package has a single row of pins?
a) SIMM
b) DIP
c) SIP
d) zig-zag

View Answer

Answer: c [Reason:] The Single-in-line package is same as that of SIMM, in which the finger connections are replaced by a single row of pins. SIP took the popularity of SIMM but nowadays it is rarely seen.

15. What is the access time of MCM51000AP10?
a) 100ns
b) 80ns
c) 60ns
d) 40ns

View Answer

Answer: a [Reason:] The access time of memory is defined as the maximum time taken by the chip to read/write data and it is very important to match the access time to the design. For example, MCM51000AP10 have 100ns access time for the memory.

Set 2

1. It retains its content when power is removed. What type of memory is this?
a) Volatile memory
b) Nonvolatile memory
c) RAM
d) SRAM

View Answer

Answer: b [Reason:] Nonvolatile devices are those which always retains it content even when any abrupt change occurs and nonvolatile memory are a kind of such devices. But RAM is a volatile memory which is a primary storage that can only access its data only when the device is powered and SRAM is a type of RAM which is called Static RAM.

2. Name a volatile memory.
a) RAM
b) EPROM
c) ROM
d) EEPROM

View Answer

Answer: a [Reason:] Volatile memory is those which can access data only when the device is powered.

3. Name a nonvolatile memory.
a) ROM
b) RAM
c) SRAM
d) DRAM

View Answer

Answer: a [Reason:] Non-volatile memory is the one which retains its content even when the power is removed. This is done by an on-chip read only memory (ROM) or an external EPROM. The software that it contains the program which is capable of obtaining the full software from another source within or outside of the system. This initialisation routine is also referred to as bootstrap program or routine.

4.The initial routine is often referred to as
a) Initial program
b) Bootstrap program
c) Final program
d) Initial embedded program

View Answer

Answer: b [Reason:] ROM contains the program which is capable of obtaining the full software from another source within or outside of the system. This initialisation routine is also referred to as bootstrap program or routine.

5. What kind of socket does an external EPROM to plugged in for prototyping?
a) Piggyback
b) Single socket
c) Multi-socket
d) Piggyback reset socket

View Answer

Answer: a [Reason:] Some controllers use a special package called piggyback socket on the top of the package to allow the EPROM for prototyping.

6. Which one of the following is UV erasable?
a) Flash memory
b) SRAM
c) EPROM
d) DRAM

View Answer

Answer: c [Reason:] EPROM is an erasable program and it can be erased by ultraviolet radiations. SRAM and DRAM are volatile memories. Flash memory to is a volatile memory but it is not UV erasable.

7. What kind of memory does an OTP have?
a) SRAM
b) RAM
c) EPROM
d) DRAM

View Answer

Answer: c [Reason:] OTP is one-time programming so it should possess a nonvolatile memory and EPROM is a nonvolatile memory whereas SRAM, DRAM and RAM are volatile memories.

8. Which type of memory is suitable for low volume production of embedded systems?
a) ROM
b) Volatile
c) Non-volatile
d) RAM

View Answer

Answer: c [Reason:] The devices which use non-volatile memory allow the software to download and returned in the device. UV erasable EPROM is favorable but EEPROM is also a gaining favor. Therefore, this type of memory is used in low volume production.

9.Which is the single device capable of providing prototyping support for a range of microcontroller?
a) ROM
b) Umbrella device
c) OTP
d) RAM

View Answer

Answer: b [Reason:] Umbrella device is capable of providing prototyping support for a range of microcontrollers.

10. What type of memory is suitable for high volume production?
a) RAM
b) ROM
c) EPROM
d) EEPROM

View Answer

Answer: b [Reason:] Read Only Memory is suitable for high volume production since it is a nonvolatile memory.

11. What type of memory is suitable for medium volume production?
a) Umbrella devices
b) OTP
c) ROM
d) RAM

View Answer

Answer: b [Reason:] One-time programmable memory is also a nonvolatile memory so it is used for medium volume production.

12. How an embedded system communicate with the outside world?
a) Peripherals
b) Memory
c) Input
d) Output

View Answer

Answer: a [Reason:] The system communicates with the outside world through peripherals.

13. How the input terminals are associated with the external environments?
a) Actuators
b) Sensors
c) Inputs
d) Outputs

View Answer

Answer: b [Reason:] Sensors measures the physical quantity and convert it into electrical means whereas actuators convert electrical quantity into physical quantity.

14. Which of the following are external pins whose logic state can be controlled by the processor to either be a logic zero or logic one is known as
a) Analogue value
b) Display values
c) Binary values
d) Time derived digital outputs

View Answer

Answer: c [Reason:] Binary values possess logic zeros and logic ones.

15. What kind of visual panel is used for seven segmented display?
a) LED
b) LCD
c) Binary output
d) Analogue output

View Answer

Answer: b

Set 3

1. How many regions are created by the memory range in the ARM architecture?
a) 4
b) 8
c) 16
d) 32

View Answer

Answer: b [Reason:] The memory protection unit in the ARM architecture divides the memory into eight separate regions. Each region can be small as well as big ranging from 4 Kbytes to 4 Gbytes.

2. How many bit does the memory region in the ARM memory protection unit have?
a) 1
b) 2
c) 3
d) 4

View Answer

Answer: c [Reason:] The memory region possesses three bits which are the cacheable bit, bufferable bit and access permission bit.

3. Which of the following uses a priority level for permitting data?
a) ARM memory management unit
b) ARM protection memory management unit
c) Bus interface unit
d) Execution unit

View Answer

Answer: b [Reason:] In the ARM protection architecture, the memory is divided into some regions of size 4 Kbytes to 4 Gbytes. These regions possess bits called the cacheable bit, buffer bit, and access permitted bits. The regions are numbered as per priority level for which the permission bits takes the precedence if any of the regions gets overlapped.

4. What type of bit in the ARM memory mimics to that of the protection unit of ARM management unit?
a) permission bit
b) buffer bit
c) cacheable bit
d) access permission bit

View Answer

Answer: a [Reason:] The ARM architecture memory protection unit divides the memory range into different regions of size ranging from 4 Kbytes to 4 Gbytes. Each region is associated with certain bits called the cacheable bit, buffer bit, and access permitted bit. These bits are similar to the permission bit in the ARM memory management unit architecture which are stored in the control register.

5. Which of the following bits are used to control the cache behaviour?
a) cacheable bit
b) buffer bit
c) cacheable bit and buffer bit
d) cacheable bit, buffer bit and permission access bit

View Answer

Answer: c [Reason:] The cacheable bit and the buffer bit are used to control the behaviour of cache. Depending on the cacheable bit and the buffer bit, the memory access will complete successfully.

6. Which of the following unit provides security to the processor?
a) bus interface unit
b) execution unit
c) peripheral unit
d) memory protection unit

View Answer

Answer: d [Reason:] The memory management unit and the memory protection unit provides security to the processor by trapping the invalid memory accesses before they corrupt other data.

7. Which of the following includes a tripped down memory management unit?
a) memory protection unit
b) memory real mode
c) memory management unit
d) bus interface unit

View Answer

Answer: a [Reason:] The memory protection unit allows a tripped memory down memory management unit in which the memories are partitioned and protected without any address translation. This can remove the time consumption in the address translation thereby increases the speed.

8. Which of the following can reduce the chip size?
a) memory management unit
b) execution unit
c) memory protection unit
d) bus interface unit

View Answer

Answer: c [Reason:] The memory protection unit have many advantages over the other units. It can reduce the chip size, cost and power consumption.

9. How does the memory management unit provide the protection?
a) disables the address translation
b) enables the address translation
c) wait for the address translation
d) remains unchanged

View Answer

Answer: a [Reason:] The memory management unit can be used as a protection unit by disabling the address translation that is, the physical address and the logical address are the same.

10. Which of the following is used to start a supervisor level?
a) error signal
b) default signal
c) wait for the signal
d) interrupt signal

View Answer

Answer: a [Reason:] If a memory access from the software does not access the correct data, an error signal is generated which will start a supervisor level software for the decision.

11. What happens when a task attempts to access memory outside its own address space?
a) paging fault
b) segmentation fault
c) wait
d) remains unchanged

View Answer

Answer: b [Reason:] Different tasks assign their own address space and whenever a task access memory outside its own address space, a segmentation fault result and which in turn results in the termination of the offending application.

Set 4

1.Which of the following microprocessor is designed by Zilog?
a) Z80
b) Zigbee
c) 80386
d) 8087

View Answer

Answer: a [Reason:] Designed by Zilog in 1976. 80386 and 8087 are the processors designed by Intel and Zigbee is IEEE based which is used for high-level communication protocol.

2. Z80 is mainly based on
a) Intel 8080
b) MIPS
c) TIMS
d) 8051

View Answer

Answer: a [Reason:] Its architecture is based on Intel 8080 but has an extended instruction set and hardware improvement.

3. Flag register of Z80 is also known as
a) Program status register
b) Program status address
c) Program status word
d) Program address register

View Answer

Answer: c [Reason:] The flag register of Z80 contains status information such as carry, overflow, signed etc.

4. What are the two register sets used in Z80?
a) C’D’ and BC’
b) CD and BD
c) IV and MR
d) Main and alternate

View Answer

Answer: d [Reason:] Z80 have two sets of registers which are main registers and alternate registers.

5. How an alternate set of the register can be identified in Z80?
a) ‘Suffix
b) ‘Prefix
c) ,suffix
d) ,prefix

View Answer

Answer: a [Reason:] In order to identify the main register and alternate register ‘ is used in the suffix.

6. What is the purpose of memory refresh register of Z80?
a) To control on-chip DRAM
b) To control on-chip SRAM
c) To control ROM
d) To clear cache

View Answer

Answer: a [Reason:] In addition to the general purpose registers, a stack pointer, program counter, and two index registers are included in Z80. It was also used in many embedded designs because of its high-quality performance and for its in-built refresh circuitry for DRAMs.

7. What is the clock frequency of Z80?
a) 6 MHz
b) 8 MHz
c) 4 MHz
d) 2 MHz

View Answer

Answer: c [Reason:] It is the maximum clock frequency or runs time of the processor.

8. Which are the two additional registers of Z80?
a) Interrupt and NMI
b) NMI and PSW
c) Interrupt vector and memory refresh
d) NMI and memory refresh

View Answer

Answer: c [Reason:] The Interrupt vector(IV) register is used in the interrupt handling. Mode 2 is used to point the required software routine to process the interrupt. In mode 1, the interrupt vector is supplied via the external data bus.

9. By which instruction does the switching of registers take place?
a) Instruction opcodes
b) AXX instruction
c) EXX instruction
d) Register instruction

View Answer

Answer: c [Reason:] Only one set of registers can be used at one time and the switching of registers and data transfer is performed by the EXX instruction.

10. Which of the following can be a paired set of 16-bit register?
a) CD
b) HL
c) AB
d) EH

View Answer

Answer: b [Reason:] Registers B, C, D,E, H and L are 8-bit general-purpose registers that can be concatenated to produce 16 registers known as BC, DE, and HL.

11. Which signal is used to differentiates the access from a normal memory cycle?
a) HALT
b) RESET
c) MREQ
d) IORQ

View Answer

Answer: d [Reason:] The IORQ signal is used to differentiate the access from a normal memory cycle. These input/output accesses are similar from a hardware perspective to a memory cycle but only occur when an input/output port instruction is executed.

12. What is done in mode1 of Z80?
a) Interrupt vector is supplied via the external bus
b) Interrupt vector is supplied via the peripherals
c) NMI gets started
d) Interrupt gets acknowledge from peripheral

View Answer

Answer: a [Reason:] In mode 1, the interrupt vector is supplied via the external data bus. The memory refresh register is used to control the on-chip DRAM refresh circuitry.

13. What does m1 signal in Z80 describes?
a) I/O operation status
b) Memory refresh output
c) Output pulse on instruction fetch cycle
d) Interrupt request input

View Answer

Answer: c [Reason:] It is a signal which describes output pulse on instruction fetch cycle. Interrupt request input, input/output operation status, memory refresh output are the other signals in Z80 for various operations.

Set 5

1. Which of the following works by dividing the processor’s time?
a) single task operating system
b) multitask operating system
c) kernel
d) applications

View Answer

Answer: b [Reason:] The multitasking operating system works by dividing the processor’s time into different discrete time slots, that is, each application requires a defined number of time slots to complete its execution.

2. Which of the following decides which task can have the next time slot?
a) single task operating system
b) applications
c) kernel
d) software

View Answer

Answer: c [Reason:] The operating system kernel decides which task can have the next time slot. So instead of the task executing continuously until completion, the execution of the processor is interleaved with the other tasks.

3. Which of the following controls the time slicing mechanism in a multitasking operating system?
a) kernel
b) single tasking kernel
c) multitasking kernel
d) application manager

View Answer

Answer: c [Reason:] The multitasking operating systems are associated with the multitasking kernel which controls the time slicing mechanism.

4. Which of the following provides time period for the context switch?
a) timer
b) counter
c) time slice
d) time machine

View Answer

Answer: c [Reason:] The time period required for each task for execution before it is stopped and replaced during a context switch is known as the time slice.

5. Which of the following can periodically trigger the context switch?
a) software interrupt
b) hardware interrupt
c) peripheral
d) memory

View Answer

Answer: b [Reason:] The multitasking operating systems are associated with the multitasking kernel which controls the time slicing mechanism. The time period required for each task for execution before it is stopped and replaced during a context switch is known as the time slice. These are periodically triggered by a hardware interrupt from the system timer.

6. Which interrupt provides system clock in the context switching?
a) software interrupt
b) hardware interrupt
c) peripheral
d) memory

View Answer

Answer: b [Reason:] The multitasking operating systems deals with the multitasking kernel which controls the time slicing mechanism and the time period required for each task for execution before it is stopped and replaced during a context switch is known as the time slice which are periodically triggered by a hardware interrupt from the system timer. This hardware interrupt provides the system clock in which several interrupts are executed and counted before a context switch is performed.

7. The special tale in the multitasking operating system is also known as
a) task control block
b) task access block
c) task address block
d) task allocating block

View Answer

Answer: a [Reason:] When a context switch is performed, the current program or task is interrupted, so the processor’s registers are saved in a special table which is known as task control block.

8. Which of the following stores all the task information that the system requires?
a) task access block
b) register
c) accumulator
d) task control block

View Answer

Answer: d [Reason:] The task control block stores all the task information that the system requires and this is done when the context switch is performed so that the currently running program is interrupted.

9. Which of the following contains all the task and their status?
a) register
b) ready list
c) access list
d) task list

View Answer

Answer: b [Reason:] The ‘ready’ list possesses all the information regarding a task, that is, all the task and its corresponding status which is used by the scheduler to decide which task should execute in the next time slice.

10. Which determines the sequence and the associated task’s priority?
a) scheduling algorithm
b) ready list
c) task control block
d) application register

View Answer

Answer: a [Reason:] The scheduling algorithm determines the sequence and an associated task’s priority. It also determines the present status of the task.

11. Which can control the memory usage?
a) operating system
b) applications
c) hardware
d) kernel

View Answer

Answer:d [Reason:] The kernel can control the memory usage and it can also prevent the tasks from corrupting each other.

12. Which can control the memory sharing between the tasks?
a) kernel
b) application
c) software
d) OS

View Answer

Answer: a [Reason:] The kernel can control memory sharing between tasks which allow sharing common program modules.

13. Which of the following can implement the message passing and control?
a) application software
b) operating system
c) software
d) kernel

View Answer

Answer: a [Reason:] The kernel can implement the message passing and control which acts as a message passer and controller between the tasks.

14. How many types of messages are associated with the real-time operating system?
a) 2
b) 3
c) 4
d) 5

View Answer

Answer: a [Reason:] There are two basic types of messages associated with the real-time operating system. These are semaphores and messages.

15. Which of the following can carry information and control task?
a) semaphore
b) messages
c) flags
d) address message

View Answer

Answer: b [Reason:] The messages can carry information and it can also control the task regarding the real-time operating systems. These are also known as events.

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