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# Multiple choice question for engineering

## Set 1

1. Which signal is sampled at regular intervals for the purpose of ADC?
a) analog signal
b) digital signal
c) quantised signal
d) sampled signal

Answer: a [Reason:] The analog signal is sampled at regular intervals for the analog to digital conversion. Each sample is then quantised to divided by a given value in order to identify the number of approximate analogue value.

2. Which factor depends the quantisation error?
a)number of error
b) number of bits
c) size of error
d) conversion process

Answer: b [Reason:] The quantisation error depends on the number of bits which is used to represent the analogue vale.

3. Which is the first type of error caused during the conversion process?
a) sampling error
b) interrupt signal
c) counter error
d) quantisation error

Answer: d [Reason:] The quantisation error is the first type of error caused in the conversion process. This error is caused because the samples are converted to a slightly higher value instead of zero.

4. Which of the following defines the number of samples that are taken in time period?
a) sample size
b) sample nature
c) sample rate
d) sample frequency

Answer: c [Reason:] The sample rate is defined by the number of samples that are taken in a time period. The sample rate is usually measured in Hertz. It can determine the speed of the conversion device itself.

5. Which of the following can determine the speed of conversion device itself.
a) sample rate
b) sampled data
c) sample size
d) sample nature

Answer: a [Reason:] The sample rate determines the various aspect of the conversion process and one such is the conversion speed.

6. Which of the following can determine the maximum frequency that can be converted?
a) sample frequency
b) sample rate
c) sample size
d) sample nature

Answer: b [Reason:] The sample rate can determine the maximum frequency that can be converted as per the Nyquist theorem. The theorem states that the minimum sampling rate frequency should be twice the maximum frequency of the analog signal.

7. Which term determines the random timing error?
a) jitter
b) quantisation error
c) sample error
d) delay

Answer: a [Reason:] Jitter is a random timing error. Jitter can cause irregular sampling errors.

8. Which of the following introduce a phase error?
a) conversion time
b) sampling rate
c) sample size
d) sample nature

Answer: a [Reason:] The conversion time always introduce a phase error. The conversion time will delay the digital output and hence introduce a phase error.

9. Which of the following can generate an interrupt?
a) timer
b) trigger
c) delay
d) counter

Answer: a [Reason:] The timer can generate an interrupt to the processor at the rate of sampling frequency.

10. Which filter is used for filtering out the high frequency components?
a) bandpass filter
b) band reject filter
c) analogue filter
d) digital filter

Answer: c [Reason:] The higher frequency components can be filtered out by using an analog filter after sampling.

11. Which theorem describes the sampling rate with the frequency of the analogue signal?
a) Nyquist theorem
b) Bayes theorem
c) Sampling theorem
d) Parseval’s theorem

Answer: a [Reason:] The Nyquist theorem states that the minimum sampling rate frequency should be twice the maximum frequency of the analog signal.

## Set 2

1. Which processors use fast interrupts?
a) DSP processor
b) RISC processor
c) CISC processor
d) Harvard processor

Answer: a [Reason:] The fast interrupts are used in the DSP processors or in microcontrollers in which a small routine is executed without saving the context of the processor.

2. Which interrupts generate fast interrupt exception?
a) internal interrupt
b) external interrupt
c) software interrupt
d) hardware interrupt

Answer: b [Reason:] The external interrupts generates the fast interrupt routine exception in which the external interrupt is synchronised with the processor clock.

3. What is the disadvantage of the fast interrupts?
a) stack frame
b) delay
c) size of routine
d) low speed

Answer: c [Reason:] The disadvantages associated with the fast interrupt is the size of routine which can be executed and the resources allocated. In this technique, it allocates a couple of address registers for the fast interrupt routine.

4. Which of the following does not have a stack frame building?
a) hardware interrupt
b) software interrupt
d) fast interrupt

Answer: d [Reason:] The fast interrupt does not have stack frame building and it does not possess any such delays. This can be considered as the advantage of the fast interrupts.

5. What is programmed to generate a two instruction fast interrupt?
a) software
b) application
c) timer
d) sensor

Answer: c [Reason:] The SCI timer generates the two instruction fast interrupt. This increment the register R1.

6. Which of the following can auto increment the register R1?
a) SCI timer
b) interrupt
c) software interrupt

Answer: a [Reason:] The SCI timer is used to generate the two instruction fast interrupt that can increment the register R1 which acts as a simple counter.

7. Which of the following forces a standard service routine?
b) IRQA interrupt
c) NMI
d) software interrupt

Answer: b [Reason:] The SCI timer is used to generate the two instruction fast interrupt which increments the register R1 that acts as a simple counter which times the period between the events. The events itself generates an IRQA interrupt, that forces the service routine.

8. Which of the following can be used as a reset button?
a) NMI
b) internal interrupt
c) external interrupt
d) software interrupt

Answer: a [Reason:] The non-maskable interrupt is used to generate an interrupt to try and recover control and therefore, the NMI can be used as a reset button.

9. Which of the following is connected to a fault detection circuit?
a) internal interrupt
b) external interrupt
c) NMI
d) software interrupt

Answer: c [Reason:] The non-maskable interrupt is used to generate an interrupt which can be connected to a fault detection circuit like watchdog timer or parity checker.

## Set 3

1. What are the three stages included in pipelining of 80386
a) Fetch, decode, execute
b) Fetch, execute, decode
c) Execute, fetch, decode
d) Decode, execute, fetch

Answer: a [Reason:] The instruction can execute in a single cycle which is done by pipelining the instruction flow. The address calculations are performed as the instruction proceeds down the line. Pipelining may take several cycles, an instruction can potentially be started and completed on every clock edge, thus achieving the single cycle performance.

2. How instructions and data are accessed to pipeline stages of 80486 processor?
a) Through internal unified cache
b) Through external unified cache
c) Through external cache
d) Through multiple caches

Answer: a [Reason:] In order to have instruction and data to the pipeline, the 80486 has an internal unified cache to contain both data and instructions. This helps in the independency of the processor on external memory.

3. Which of the following processor possesses a similar instruction of 80486?
a) 8086
b) 80286
c) 80386
d) 8080

Answer: c [Reason:] The instruction set is same as that of 80386 but there are some additional instructions available when the processor is in protected mode.

4. What are the two external interrupt signals in 80386?
a) IV and NMI
b) NMI and INTR
c) INTR and IV
d) PC and NMI

Answer: b [Reason:] The 80386 has two external interrupt signals which allow external devices to interrupt the processor. The INTR input creates a maskable interrupt while the NMI creates a non-maskable interrupt.

5. How many bit vector number is used in an interrupt cycle of 80386?
a) 4
b) 8
c) 16
d) 32

Answer: b [Reason:] While an interrupt cycle is running, the processor possesses two interrupts acknowledge bus cycles and reads an 8-bit vector number. This vector is then used to locate, within the vector table and it has the address of the corresponding interrupt service routine. NMI is automatically assigned as vector number 2.

6. In how many modes does 80386 can run?
a) 2
b) 4
c) 3
d) 5

Answer: c [Reason:] The 80386 can run in three different modes: the real mode, the protected mode, and a virtual mode. In real mode, the size of each segment is limited to 64 Kbytes and in protected mode, the largest segment size is increased to 4 Gbytes and the virtual mode is a special version of the protected mode.

7. How many bit flag register does 80386 have?
a) 8
b) 16
c) 32
d) 64

Answer: c [Reason:] The 32-bit flag register possesses the normal carry zero, auxiliary carry, parity, sign and overflow flags.

8. Which processor is the derivative of 80386DX?
a) 80387
b) 80386SX
c) 80386 DDX
d) 8087

Answer: b [Reason:] Derivative of the 80386DX called the 80386SX which provides the same architecture and lowers cost. To minimal the cost value, it uses an external 16-bit data bus and a 24-bit memory bus.

9. Which of the following is a portable device of Intel?
a) 80386DX
b) 8087
c) 80386SL
d) 80386SX

Answer: c [Reason:] Intel has 80386SL as the portable PCs which helps in controlling power and increases the power efficiency of the processor.

10. Which of the processor has a 5 stage pipeline?
a) 80386
b) 80486
c) 80286
d) 80386DX

Answer: b [Reason:] 80486 have a five stage pipeline ALU. These include fetch, decode, execute, memory access and write back. This helps in accessing instruction faster and thus makes the processor faster. 80386DX have a three-stage pipelining which only includes fetch, decode and execute.

11. Which of the following processor can execute two instructions per cycle?
a) 80486
b) 80386DX
c) Intel Pentium
d) 80386

Answer: c [Reason:] Intel Pentium have many advanced features one of which is, it can execute two instructions per cycle thus improving the speed of the processor whereas 80486, 80386 and 80386DX does not have this feature.

12. Which of the following processors have two five-stage pipelines?
a) 80486
b) 80386
c) Intel Pentium
d) 80386DX

Answer: c [Reason:] The intel Pentium possess two five-stage pipelines which allow the execution of two integer instruction jointly.

13. In which processor does the control register and system management mode register first appeared?
a) 80386
b) 80386SL
c) 80386DX
d) 80486

Answer: b [Reason:] The control register and system management mode register has first appeared in 80386SL and later on succeeded by other processors. These registers can provide intelligent power control.

14. Which is the next successor of Intel Pentium?
a) Pentium pro
b) P1
c) P2
d) P5

Answer: a [Reason:] Intel Pentium is succeeded by Pentium pro. P1, P2, and P5 are the other processors of Intel.

15. Which of the following processor allows a multiple branch prediction?
a) 80386
b) P1
c) Intel Pentium
d) Intel Pentium pro

Answer: d [Reason:] A branch instruction can change the program flow and multiple branch prediction allows the continuous execution of instructions based on assumptions. This can eliminate delay and thus speeds up the execution.

## Set 4

1. How many data lines does 256*4 have?
a) 256
b) 8
c) 4
d) 32

Answer: c [Reason:] There are four data lines in the memory and these different organisations of memory and these different organisations of memory are apparent when upgrading memory and it also determines how many chips are needed.

2. How is the number of chips required is determined?
a) number of data lines
b) the minimum number of data
c) width of the data path from the processor
d) number of data lines and the width of the data path from the processor

Answer: d [Reason:] The minimum number of chips is determined by the number of data lines and the width of the data path from the processor. For example, MC6800 family have a 16-bit wide datapath, 16*1 devices, 4*4 or 2*8 devices are needed.

3. Where is memory address stored in a C program?
a) stack
b) pointer
c) register
d) accumulator

Answer: b [Reason:] Memory model is defined by a range of memory address which is accessible to the program. For example, in C program, the memory address is stored in the pointer.

4. Which is the term that is used to refer the order of bytes?
a) endianness
b) memory organisation
c) bit
d) register

Answer: a [Reason:] Endianness defines the order of bytes, that is, whether it is big endian or little endian. The former represents the higher order bits and the latter represents the lower order bits.

5. Which of the following processors uses big endian representation?
a) 8086
b) ARM
c) PowerPC
d) Zilog Z80

Answer: c [Reason:] The IBM’s PowerPC uses big endian representation whereas 8086,ARM and Zilog Z80 uses little representation.

6. Which statement is true for a cache memory?
a) memory unit which communicates directly with the CPU
b) provides backup storage
c) a very high-speed memory to increase the speed of the processor
d) secondary storage

Answer: c [Reason:] The RAM is the primary storage which directly communicates with the CPU. ROM is the secondary storage. Disk drives are capable of providing backup storage and the cache memory is a small high-speed memory which increases the speed of the processor.

7. Which of the following memory organisation have the entire memory available to the processor at all times?
b) paging

Answer: d [Reason:] There are two types of memory organisation, linear addressing in which the entire memory is available to the processor of all times as in Motorola 6800 and the other is segmented addressing where the memory space is divided into several segments and the processor is limited to access the program instructions and data which are located in particular segments.

8. How many memory locations can be accessed by 8086?
a) 1 M
b) 2 M
c) 3 M
d) 4 M

Answer: a [Reason:] The 8086 processor has a 20-bit address bus, hence it can access a memory of 220-1 M locations.

9. Which of the is a memory that is allocated to the program in LIFO pattern?
a) stack
b) index
c) accumulator
d) base

Answer: a [Reason:] A stack is a memory which is allocated to the program in last-in, first out pattern. Stack pointer contains the memory address of the stack.

10. What does SIMM stand for?
a) single in-line memory module
b) single interrupt memory module
c) single information memory module
d) same-in-line memory module

Answer: a [Reason:] SIMM is single in-line memory module is a kind of memory module, which contains random access memory used in computers of the early 1980s and 1990s.

11. Which of the memory organisation is widely used in parity bit?
a) by 1 organisation
b) by 4 organisation
c) by 8 organisation
d) by 9 organisation

Answer: a [Reason:] The use of By 1 organisation is declined because of the wider data path devices. But it is still used in parity bit and were used in SIMM memory.

12. Which configuration of memory organisation replaces By 1 organisation?
a) by 4 organisation
b) by 8 organisation
c) by 9 organisation
d) by 16 organisation

Answer: a [Reason:] By 1 organisation is replaced with By 4 organisation because of its reduced address bus and complexity.

13. Which shifting helps in finding the physical address in 8086?
a) shifting the segment by 8
b) shifting the segment by 6
c) shifting the segment by 4
d) shifting the segment by 2

Answer: c [Reason:] The address bus of the 8086 is 20-bit and the data bus is 16-bit in size. So the physical address can be calculated by shifting the segment register by 4 to left and by adding the address bus to it.

14. Which memory organisation is supported in wider memories?
a) by 8 organisation
b) by 16 organisation
c) by 9 organisation
d) by 4 organisation

Answer: b [Reason:] The wider memories support 16-bits because it can integrate more number of the interface logic so that the time consumed by the latches and buffers removes the memory access thus allowing the slower parts to be used in wait state free designs.

15. Which of the following is a plastic package used primarily for DRAM?
a) SIMM
b) DIMM
c) Zig-zag
d) Dual-in-line

Answer: c [Reason:] Zig-zag package of memory is a plastic package used for DRAM. The leads of this package are arranged in a zigzag manner.

## Set 5

1. What does I2C stand for?
a) inter-IC
b) intra-IC
c) individual integrated chip
d) intel IC

Answer: a [Reason:] The I2C is known as inter-IC, which is developed by Philips for interfacing with the peripheral devices.

2. Which company developed I2C?
a) Intel
b) Motorola
c) Phillips
d) IBM

Answer: c [Reason:] The I2C is developed by Philips for use within the television sets.

3. Which of the following is the most known simple interface?
a) I2C
b) Serial port
c) Parallel port
d) SPI

Answer: a [Reason:] The I2C is the most known simple interface which is used currently. It can combine both the hardware and the software protocols to provide a bus interface which helps in the communication with many peripherals.

4. Which are the two lines used in the I2C?
a) SDA and SPDR
b) SPDR and SCL
c) SDA and SCL
d) SCL and status line

Answer: c [Reason:] The I2C bus consists of two lines which are called SDA and SCL. The master and slave devices are attached to these lines.

5. Which of the following developed P82B715?
a) Philips
b) Intel
c) IBM
d) Motorola

Answer: a [Reason:] The special buffer chip, P82B715 for increasing the current drive is developed by Philips.

6. Which pin provides the reference clock for the transfer of data?
a) SDA
b) SCL
c) SPDR
d) Interrupt pin

Answer: b [Reason:] The SCL pin can provide the reference clock for the transmission of data but it is not a free running clock.

7. Which of the following are the three hardware signals?
a) START, STOP, ACKNOWLEDGE
b) STOP, TERMINATE, END
c) START, SCL, SDA
d) STOP, SCL, SDA

Answer: a [Reason:] The three hardware signals are START, STOP and ACKNOWLEDGE. These signals helps in the transmission of data between the slave and the masters.

8. Which of the following performs the START signal?
a) master
b) slave
c) CPU
d) memory

Answer: a [Reason:] The START signal is performed by the master by making the SCL and SDA pin high.

9. Which of the following are handshake signal?
a) START
b) STOP
c) ACKNOWLEDGE
d) START and STOP

Answer: c [Reason:] The START signal and ACKNOWLEDGE signals are almost similar but there exhibits a small change. The START signal is initiated by the master only but the ACKNOWLEDGE signal is a handshake between both the master and slave.

10. A packet is also referred to as
a) postcard
b) telegram
c) letter
d) data