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Multiple choice question for engineering

Set 1

1. Which of the following kernel supports the MC68000 family?
a) pSOS+
b) pSOS+kernel
c) pNA+ network manager
d) pSOS multiprocessor kernel

View Answer

Answer: a [Reason:] The pSOS+ kernel supports many processor families like Intel 80×86, M88000, MC68000 and i960 processors. The kernel is small in size and has a 15-20 Kbytes RAM.

2. What is the worst case figure for interrupt latency for an MC68020 running at 25MHz?
a) 19 microseconds
b) 6 microseconds
c) 20 microseconds
d) 8 microseconds

View Answer

Answer: b [Reason:] The worst case figure for the interrupt latency for an MC68020 which runs at 25MHz is 6 microseconds and the context switch for the same is 19 microseconds.

3. Which of the following is the multiprocessing version of the kernel?
a) pSOS+
b) pSOS+ kernel
c) pSOS multiprocessor kernel
d) pSOS

View Answer

Answer: c [Reason:] The pSOS+ is a multitasking real-time kernel of the operating system and pSOS+m or the pSOS+ multiprocessor kernel is the multiprocessing version of the kernel. It is virtually same as the single processor version except the ability to send and receiving system objects from the processors within the system.

4. Which of the following is a compiler independent run-time environment for C applications?
a) pSOS multiprocessor kernel
b) pSOS
c) pSOS+
d) pREC+ runtime support

View Answer

Answer: d [Reason:] The pREC+ is a compiler independent runtime environment for the C program applications.

5. Which kernel provides 88 functions that can be called from the C programs?
a) pSOS multiprocessor kernel
b) pSOS
c) pSOS+
d) pREC+ runtime support

View Answer

Answer: d [Reason:] The pREC+ is compatible with the ANSI X3J11 and can provide the 88 functions that can be called from the C programs.

6. Which of the following is not a standalone product?
a) pREC+ runtime support
b) pSOS+m
c) pSOS+
d) pSOS+ kernel

View Answer

Answer: a [Reason:] The pREC+ is not a standalone product it uses pSOS+m or pSOS+ for the input/output devices and task functions and calls the PHILE+ for the file and disk I/O.

7. Which kernel allows the multiple tasks which use the same routine?
a) pREC+ runtime support
b) pSOS+m
c) pSOS+
d) pSOS+ kernel

View Answer

Answer: a [Reason:] The pREC+ runtime support kernel’s routines are reentrant that allows the multiple tasks to use the same routine simultaneously.

8. Which provides the TCP/IP communication over the ethernet and FDDI?
a) pSOS+m
b) pSOS+ kernel
c) pNA+ network manager
d) pSOS+

View Answer

Answer: c [Reason:] The pNA+ network manager is a networking option which can provide the TCP/IP communication over a large variety of media such as the FDDI and the ethernet.

Set 2

1. Which of the following is a coprocessor of 80386?
a) 80387
b) 8087
c) 8089
d) 8088

View Answer

Answer: a [Reason:] 80386 have 80387 as a floating point arithmetic coprocessor which can perform various floating point calculations.

2. Name the processor which helps in floating point calculations.
a) microprocessor
b) microcontroller
c) coprocessor
d) controller

View Answer

Answer: c [Reason:] The coprocessor can perform signal processing, floating point arithmetics, encryption etc.

3. Which is the coprocessor of 8086?
a) 8087
b) 8088
c) 8086
d) 8080

View Answer

Answer: a [Reason:] 8087 is the coprocessor for both 8086 and 8088. 8089 is also a coprocessor of 8086 and 80888.

4. Which of the following is a coprocessor of Motorola 68000 family?
a) 68001
b) 68011
c) 68881
d) 68010

View Answer

Answer: c [Reason:] The 68881 coprocessor of Motorola provides floating point arithmetics.

5. Which of the following processors can perform exponential, logarithmic and trigonometric functions?
a) 8086
b) 8087
c) 8080
d) 8088

View Answer

Answer: b [Reason:] 8087 is a coprocessor which can perform all the mathematical functions including addition, subtraction, multiplication, division, exponential, logarithmic, trigonometric etc. 8086, 8080 and 8088 are microprocessors which require the help of a coprocessor for floating point arithmetic.

6. How many stack register does an 8087 have?
a) 4
b) 8
c) 16
d) 32

View Answer

Answer: b [Reason:] The 8087 coprocessor does not have a main register set but they have an 8-level deep stack register from st0 to st7.

7. Which of the following processor can handle infinity values?
a) 8080
b) 8086
c) 8087
d) 8088

View Answer

Answer: c [Reason:] 8087 is a coprocessor which can handle infinity values with two types of closure known as affine closure and projective closure.

8. Which coprocessor supports affine closure?
a) 80187
b) 80287
c) 80387
d) 8088

View Answer

Answer: b [Reason:] 80287 uses an affine closure for infinity values whereas 80387 and 80187 support projective closure for infinity values.

9. Which one is the floating point coprocessor of 80286?
a) 8087
b) 80187
c) 80287
d) 80387

View Answer

Answer: c [Reason:] 80286 supports 80287 as its floating point coprocessor which helps in floating point calculations.

10. How many pins does 8087 have?
a) 40 pin DIP
b) 20 pin DIP
c) 40 pins
d) 20 pins

View Answer

Answer: a [Reason:] All 8087 models have a 40 pin DIP which is operated in 5V.

11. What is the clock frequency of 8087?
a) 10 MHz
b) 5 MHz
c) 6 MHz
d) 4 MHz

View Answer

Answer: b [Reason:] 8087 have 5 MHz as its clock frequency because the coprocessor must have the same clock frequency as that of the main processor.

12. How are negative numbers stored in a coprocessor?
a) 1’s complement
b) 2’s complement
c) decimal
d) gray

View Answer

Answer: b [Reason:] In a coprocessor, negative numbers are stored in 2’s complement with its leftmost sign bit of 1 whereas positive numbers are stored in the form of true value with its leftmost sign bit of 0.

13. How many bits are used for storing signed integers?
a) 2
b) 4
c) 8
d) 16

View Answer

Answer: d [Reason:] Signed integers in a coprocessor are stored as 16-bit word, 32-bit double word or 64-bit quadword.

14. Which of the processor has an internal coprocessor?
a) 8087
b) 80287
c) 80387
d) 80486DX

View Answer

Answer: d [Reason:] 8087 is an external IC designed to operate with the 8088/8086 processor but 80486DX is an on-chip coprocessor that is, it does not require an extra integrated chip for floating point arithmetics.

15. What are the two major sections in a coprocessor?
a) control unit and numeric control unit
b) integer unit and control unit
c) floating point unit and coprocessor unit
d) coprocessor unit and numeric control unit

View Answer

Answer: a [Reason:] Control unit interfaces the coprocessor with its main microprocessor whereas numeric control unit can execute the coprocessor instructions.

Set 3

1. Which of the following provides an efficient method for transferring data from a peripheral to memory?
a) dma controller
b) serial port
c) parallel port
d) dual port

View Answer

Answer: a [Reason:] The DMA controllers or direct memory access controller provides an efficient method for transferring data from the peripheral to the memory.

2. Which of the following can be adopted for the systems which does not contain DMA controller for data transmission?
a) counter
b) timer
c) polling
d) memory

View Answer

Answer: c [Reason:] The polling and interrupt helps for data transmission for the systems which do not have DMA controller.

3. Which of the following have low-level buffer filling?
a) output
b) peripheral
c) DMA controller
d) input

View Answer

Answer: c [Reason:] The DMA controller can initiate and control the bus access between I/O devices and memory, and also between two different memory areas. Therefore, the DMA controller can act as a hardware implementation of low-level buffer filling or emptying the interrupt.

4. How many classifications of DMA controllers are made based on the addressing capability?
a) 2
b) 3
c) 4
d) 5

View Answer

Answer: b [Reason:] There are three classifications for the DMA controllers based on the address capability. These are 1D, 2D and 3D.

5. How many address register are there for the 1D type DMA controller?
a) 1
b) 2
c) 3
d) 4

View Answer

Answer: a [Reason:] The 1D controller only have a single address register whereas 2D controller have two address register and 3D controller have three or more address register.

6. Which of the following of a generic DMA controller contain a base address register and an auto-incrementing counter?
a) address bus
b) data bus
c) bus requester
d) address generator

View Answer

Answer: d [Reason:] The generic controller have several components associated with it for controlling the operation and one such is the address generator. It consists of the base address register and an auto-incrementing counter which increment the address after every transfer.

7. Which of the following is used to transfer the data from the DMA controller to the destination?
a) data bus
b) address bus
c) request bus
d) interrupt signal

View Answer

Answer: a [Reason:] The data bus is used for the transmission of data from the DMA controller to the destinal. The DMA controller can directly select the peripheral in some cases in which the data transfer is made from the peripheral to the memory.

8. Which of the following is used to request the bus from the main CPU?
a) data bus
b) address bus
c) bus requester
d) interrupt signal

View Answer

Answer: c [Reason:] The bus requester requests the bus from the main CPU. In earlier design, the processor bus does not support the multi master system and there were no bus request signals. In such cases, the processor clock was extended.

9. Which signal can identify the error?
a) data bus
b) address bus
c) bus requester
d) interrupt signal

View Answer

Answer: d [Reason:] The interrupt signal can identify the error occurred in the DMA controller. This makes the processor to reprogram the DMA controller for a different transfer.

10. Which signal allows the DMA controller to select the peripheral?
a) local peripheral control
b) global peripheral control
c) address bus
d) data bus

View Answer

Answer: a [Reason:] The local peripheral control allows the DMA controller to select the peripheral.

Set 4

1. Which memory storage is widely used in PCs and Embedded Systems?
a) SRAM
b) DRAM
c) Flash memory
d) EEPROM

View Answer

Answer: b [Reason:] DRAM is used in PCs and Embedded systems because of its low cost. SRAM, flash memory and EEPROM are more costly than DRAM.

2. Which of the following memory technology is highly denser?
a) DRAM
b) SRAM
c) EPROM
d) Flash memory

View Answer

Answer: a [Reason:] DRAM is highly denser and cheaper because it only uses a single capacitor for storing one bit.

3. Which is the storage element in DRAM?
a) inductor
b) capacitor
c) resistor
d) mosfet

View Answer

Answer: b [Reason:] DRAM uses a small capacitor whose voltage represents a binary zero which is used a storage element in DRAM in which a single transistor cell is used to store each bit of data.

4. Which one of the following is a storage element in SRAM?
a) capacitor
b) inductor
c) transistor
d) resistor

View Answer

Answer: c [Reason:] Four to six transistors are used to store a single bit of data and form a flip-flop logic gate and thus SRAM is faster in accessing data.

5. Which of the following is more volatile?
a) SRAM
b) DRAM
c) ROM
d) RAM

View Answer

Answer: b [Reason:] DRAM is said to be more volatile because it has a capacitor as its storage element in which the data disappears when the capacitor loses its charge so even when the device is powered the data can be lost.

6. What is the size of a trench capacitor in DRAM?
a) 1 Mb
b) 4-256 Mb
c) 8-128 Mb
d) 64-128 Mb

View Answer

Answer: b [Reason:] Trench capacitor can store from 4-256 Mb but planar capacitor can store up to 1 Mb.

7. Which of the following capacitor can store more data in DRAM?
a) planar capacitor
b) trench capacitor
c) stacked-cell
d) non-polar capacitor

View Answer

Answer: c [Reason:] Stacked-cell can store greater than 1 Gb. Planar capacitor can store up to 1 Mb and trench capacitor can store 4-256 Mb.

8. In which of the memories, does the data disappears?
a) SRAM
b) DRAM
c) Flash memory
d) EPROM

View Answer

Answer: b [Reason:] Both SRAM and DRAM are volatile memories and flash memory and EPROM are non-volatile memories. DRAM has storage element as a capacitor whose charge loses gradually thereby losing data.

9. Which of the following is the main factor which determines the memory capacity?
a) number of transistors
b) number of capacitors
c) size of the transistor
d) size of the capacitor

View Answer

Answer: a [Reason:] The chip capacity is dependent on the number of transistors which can be fabricated on the silicon, and DRAM offers more storage capacity than SRAM.

10. What does VRAM stand for?
a) video RAM
b) verilog RAM
c) virtual RAM
d) volatile RAM

View Answer

Answer: a [Reason:] Video RAM is a derivative of DRAM. It functions like a DRAM and has additional functions to access data for video hardware for creating the display.

11. What does TCR stand for?
a) temperature-compensated refresh
b) temperature-compensated recovery
c) texas CAS-RAS
d) temperature CAS-RAS

View Answer

Answer: a [Reason:] The temperature-compensated refresh is one of the refreshing techniques used for extending the battery life by reducing the refresh rate.

Set 5

1. In which pin does the data appear in the basic DRAM interfacing?
a) dout pin
b) din pin
c) clock
d) interrupt pin

View Answer

Answer: a [Reason:] In the basic DRAM interfacing, the higher order bits asserts the RAS signal and the lower order bits asserts the CAS signal. When the access got expired, the data appears on the dout pin and is latched by the processor.

2. What is the duration for memory refresh to remain compatible?
a) 20 microseconds
b) 12 microseconds
c) 15 microseconds
d) 10 microseconds

View Answer

Answer: b [Reason:] The memory refresh is performed every 15 microseconds in order to remain compatible.

3. Which interfacing method lowers the speed of the processor?
a) basic DRAM interface
b) page mode interface
c) page interleaving
d) burst mode interface

View Answer

Answer: a [Reason:] The direct method access limits the wait state-free operation which lowers the processor speed.

4. What is EDO RAM?
a) extreme data operation
b) extended direct operation
c) extended data out
d) extended DRAM out

View Answer

Answer: c [Reason:] EDO RAM is a special kind of random access memory which can improve the time to read from the memory on faster microprocessors. The example of such a microprocessor is Intel Pentium.

5. What is RDRAM?
a) refresh DRAM
b) recycle DRAM
c) Rambus DRAM
d) refreshing DRAM

View Answer

Answer: c [Reason:] Rambus DRAM is a synchronous memory developed by Rambus. It can replace SDRAM and is useful in high bandwidth applications.

6. Which of the following can transfer up to 1.6 billion bytes per second?
a) DRAM
b) RDRAM
c) EDO RAM
d) SDRAM

View Answer

Answer: b [Reason:] The Rambus RAM can transfer up to 1.6 billion bytes per second. It possesses RAM controller, a bus which connects the microprocessor and the device, and a random access memory.

7. Which of the following cycle is larger than the access time?
a) write cycle
b) set up time
c) read cycle
d) hold time

View Answer

Answer: c [Reason:] The read cycle in the DRAM interfacing is larger than the access time because of the precharge time.

8. Which mode of operation selects an internal page of memory in the DRAM interfacing?
a) page interleaving
b) page mode
c) burst mode
d) EDO RAM

View Answer

Answer: b [Reason:] In the page mode operation, the row address is provided as normal but the RAS signal is left asserted. This, in turn, selects an internal page within the DRAM memory where any bit of data can be accessed by placing the column address and asserting CAS.

9. What is the maximum time that the RAS signal can be asserted in the page mode operation?
a) 5 microseconds
b) 10 microseconds
c) 15 microseconds
d) 20 microseconds

View Answer

Answer: b [Reason:] The maximum time that the RAS signal can be asserted during the page mode operation is about 10 microseconds. But this is a major disadvantage for page mode operation, that is, the standard PCs have a maximum time of 15 microseconds for the refresh cycle.

10. Which of the following mode of operation in the DRAM interfacing has a page boundary?
a) burst mode
b) EDO RAM
c) page mode
d) page interleaving

View Answer

Answer: c [Reason:] The page mode operation have memory cycles that exhibit some form of locality, that is, stay within the page boundary which causes page missing when there is an access outside the page boundary and two or more wait states.

11. Which mode offers the banking of memory in the DRAM interfacing technique?
a) page mode
b) basic DRAM interfacing
c) page interleaving
d) burst mode

View Answer

Answer: c [Reason:] The accessing of data outside the page boundary can cause missing of pages in the page mode operation. So a program has to operate for frequently accessing data thereby, increasing the efficiency in the page selection. One such mode is the page interleaving mode in which the memory is divided into different banks, depending on the number of memories installed.

12. Which of the following has a fast page mode RAM?
a) burst mode
b) page interleaving
c) EDO memory
d) page mode

View Answer

Answer: c [Reason:] Extended data out memory is a fast page mode RAM which has a faster cycling process which makes EDO memory a faster page mode access.

13. Which mode reduces the need for fast static RAMs?
a) page mode
b) page interleaving
c) burst mode
d) EDO memory

View Answer

Answer: c [Reason:] The page mode, nibble mode devices can provide data fastly when the new column address is given. In burst mode operation, the processor can fetch more data than it needs and keeps the remaining data in an internal cache for the future use which can reduce the need for fast static RAMs.

14. Which of the following is also known as hyper page mode enabled DRAM?
a) page mode
b) EDO DRAM
c) burst EDO DRAM
d) page interleaving

View Answer

Answer: b [Reason:] The EDO DRAM is also known as hyper page mode enable DRAM because of the faster page mode operation along with some additional features.

15. What does BEDO DRAM stand for?
a) burst EDO DRAM
b) buffer EDO DRAM
c) BIBO EDO DRAM
d) bilateral EDO DRAM

View Answer

Answer: a [Reason:] The burst EDO DRAM is evolved from the EDO DRAM and it can access four memory addresses in one burst. It also supports pipeline stages which allow the page access cycle into two parts.