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Multiple choice question for engineering

Set 1

1. Which of the following include special address generation and data latches?
a) burst interface
b) peripheral interface
c) dma
d) input-output interfacing

View Answer

Answer: a [Reason:] The burst interfacing has special memory interfaces which include special address generation and data latches that help in the high performance of the processors. It takes the advantages of both the nibble mode memories and paging.

2. Which of the following makes use of the burst fill technique?
a) burst interfaces
b) dma
c) peripheral interfaces
d) input-output interfaces

View Answer

Answer: a [Reason:] The burst interfaces uses the burst fill technique in which the processor will access four words in succession, which fetches the complete cache line or written out to the memory.

3. How did burst interfaces access faster memory?
a) segmentation
b) dma
c) static column memory
d) memory

View Answer

Answer: c [Reason:] The speed of the memory can be improved by the page mode or the static column memory which offer a faster access in a single cycle.

4. Which of the following memory access can reduce the clock cycles?
a) bus interfacing
b) burst interfacing
c) dma
d) dram

View Answer

Answer: b [Reason:] The burst interfaces reduces the clock cycles. For fetching four words with a three clock memory, it will take 12 clock cycle but in the burst interface, it will only take five clocks to access the data.

5. How many clocks are required for the first access in the burst interface?
a) 1
b) 2
c) 3
d) 4

View Answer

Answer: b [Reason:] In the burst interface, the first access of the memory address requires two clock cycles and single cycle for the remaining memory address.

6. In which of the following access, the address is supplied?
a) the first access
b) the second access
c) third access
d) fourth access

View Answer

Answer: a [Reason:] In the burst interface, the address is supplied only for the first access and not for the remaining accesses. An external logic is required for the additional addresses for the memory interface.

7. What type of timing is required for the burst interfaces?
a) synchronous
b) equal
c) unequal
d) symmetrical

View Answer

Answer: c [Reason:] The burst interfacing uses an unequal timing. It takes two clocks for the first access and only one for the remaining accesses which make it an unequal timing.

8. How can gate delays be reduced?
a) synchronous memory
b) asynchronous memory
c) pseudo asynchronous memory
d) symmetrical memory

View Answer

Answer: a [Reason:] The burst interfaced is associated with the SRAM and for the efficiency of the SRAM, it uses a synchronous memory on-chip latches to reduce the gate delays.

9. In which memory does the burst interfaces act as a part of the cache?
a) DRAM
b) ROM
c) SRAM
d) Flash memory

View Answer

Answer: c [Reason:] The burst interface is associated with the static RAM.

10. Which of the following uses a wrap around burst interfacing?
a) MC68030
b) MC68040
c) HyperBus
d) US 5729504 A

View Answer

Answer: b [Reason:] MC68040 is developed by the Motorola which uses a wrap around burst interfacing. MC68030 is also developed by Motorola but it uses a linear line fill burst. HyperBus can switch to both linear and wrap around burst. US 5729504 A uses a linear burst fill.

11. Which of the following is a Motorola’s protocol product?
a) MCM62940
b) Avalon
c) Slave interfaces
d) AXI slave interfaces

View Answer

Answer: a [Reason:] MCM62940 protocol is developed by Motorola, whereas Slave interfaces, AXI slave interfaces are for ARM. Avalon is developed by Altera.

12. Which of the following uses a linear line fill interfacing?
a) MC68040
b) MC68030
c) US 74707 B2
d) Hyper Bus

View Answer

Answer: b [Reason:] MC68030 uses a linear burst fill whereas MC68040, US 74707 B2 uses to wrap around burst interfacing. HyperBus can switch to both linear and wrap around interfacing.

13. Which of the following protocol matches the Intel 80486?
a) MCM62940
b) MCM62486
c) US 74707 B2
d) Hyper Bus

View Answer

Answer: b [Reason:] The MCM62486 has an on-chip counter that matches the Intel 80486 and is developed by the Motorola.

14. Which of the following protocol matches the MC68040?
a) MCM62486
b) US 5729504 A
c) HyperBus
d) MCM62940

View Answer

Answer: d [Reason:] The MCM62940 and MCM62486 are the specific protocols developed by Motorola, in which the MCM62940 has an on-chip counter which matches the wrap-around burst interfacing of the MC68040.

Set 2

1. Which of the following is more quickly accessed?
a) RAM
b) Cache memory
c) DRAM
d) SRAM

View Answer

Answer: b [Reason:] The cache memory is a small random access memory which is faster than a normal RAM. It has a direct connection with the CPU otherwise, there will be a separate bus for accessing data. The processor will check whether the copy of the required data is present in the cache memory if so it will access the data from the cache memory.

2. Which factor determines the effectiveness of cache?
a) hit rate
b) refresh cycle
c) refresh rate
d) refresh time

View Answer

Answer: a [Reason:] The proportion of accesses of data that forms the cache hit, which measures the effectiveness of the cache memory.

3. Which of the following determines a high hit rate of the cache memory?
a) size of the cache
b) number of caches
c) size of the RAM
d) cache access

View Answer

Answer: a [Reason:] The size of the cache increases, a large amount of data can be stored, which can access more data which in turn increases the hit rate of the cache memory.

4. Which of the following is a common cache?
a) DIMM
b) SIMM
c) TLB
d) Cache

View Answer

Answer: c [Reason:] The translation lookaside buffer is common cache memory seen in almost all CPUs and desktops which are a part of the memory management unit. It can improve the virtual address translation speed.

5. Which factor determines the number of cache entries?
a) set commutativity
b) set associativity
c) size of the cache
d) number of caches

View Answer

Answer: b [Reason:] The set associativity is a criterion which describes the number of cache entries which could possibly contain the required data.

6. What is the size of the cache for an 8086 processor?
a) 64 Kb
b) 128 Kb
c) 32 Kb
d) 16 Kb

View Answer

Answer: a [Reason:] The 8086 processor have a 64 Kbytes cache, beyond this size, the cost will be extremely high.

7. How many possibilities of mapping does a direct mapped cache have?
a) 1
b) 2
c) 3
d) 4

View Answer

Answer: a [Reason:] The direct mapped cache only have one possibility to fetch data whereas a two-way system, there are two possibilities, for a three-way system, there are three possibilities and so on. It is also known as the one-way set associative cache.

8. Which of the following allows speculative execution?
a) 12-way set associative cache
b) 8-way set associative cache
c) direct mapped cache
d) 4-way set associative cache

View Answer

Answer: c [Reason:] The direct mapped cache has the advantage of allowing a simple and fast speculative execution.

9. Which of the following refers to the number of consecutive bytes which are associated with each cache entry?
a) cache size
b) associative set
c) cache line
d) cache word

View Answer

Answer: c [Reason:] The cache line refers to the number of consecutive bytes which are associated with each cache entry. The data is transferred between the memory and the cache in a particular size which is called cache line.

10. Which factor determines the cache performance?
a) software
b) peripheral
c) input
d) output

View Answer

Answer: a [Reason:] The cache performance is completely dependent on the system and software. In software, the processor checks out each loop and if a duplicate is found in the cache memory, immediately it is accessed.

11. What are the basic elements required for cache operation?
a) memory array, multivibrator, counter
b) memory array, comparator, counter
c) memory array, trigger circuit, a comparator
d) memory array, comparator, CPU

View Answer

Answer: b [Reason:] The cache memory operation is based on the address tag, that is, the processor generates the address which is provided to the cache and this cache stores its data with an address tag. The tag is compared with the address, if they did not match, the next tag is checked. If they match, a cache hit occurs, the data is passed to the processor. So the basic elements required is a memory array, comparator, and a counter.

12. How many divisions are possible in the cache memory based on the tag or index address?
a) 3
b) 2
c) 4
d) 5

View Answer

Answer: c [Reason:] There is four classification based on the tag or index address corresponds to a virtual or physical address. They are PIPT, VIVT, PIVT, VIPT that is, physically indexed physically tagged, virtually indexed virtually tagged, physically indexed virtually tagged, virtually indexed physically tagged respectively.

13. What does DMA stand for?
a) direct memory access
b) direct main access
c) data main access
d) data memory address

View Answer

Answer: a [Reason:] The DMA is direct memory access which can modify the memory without the help of the processor. If any kind of memory access by DMA to be done, it will passes a request to the processor bus and the processor provides an acknowledgement and gives the control of the bus to the DMA.

Set 3

1. Which mode of the Intel timer 8253 provides a software watchdog timer?
a) rate generator
b) hardware triggered strobe
c) square wave rate generator
d) software triggered strobe

View Answer

Answer: d [Reason:] The software triggered strobe can be used as a software-based watchdog timer in which the output is connected to a non maskable interrupt.

2. Which of the following mode is similar to the mode 4 of the 8253 timer?
a) mode 5
b) mode 6
c) mode 0
d) mode 1

View Answer

Answer: a [Reason:] The mode 5 or the hardware triggered strobe is similar to the mode 4 or the square wave rate generator expect that the retriggering is done by the external gate pin.

3. Which pin of 8253 is used for the generation of an external interrupt signal?
a) OUT pin
b) IN pin
c) Interrupt pin
d) Ready pin

View Answer

Answer: a [Reason:] The Intel 8253 timer has no interrupt pins. Therefore, the timer OUT pin is used to generate an external interrupt signal.

4. Which timer architecture can provide a higher resolution than Intel 8253?
a) Intel 8253
b) Intel 8254
c) 8051 timer
d) MC68230

View Answer

Answer: d [Reason:] The Intel 8253 and 8254 have same pin configuration and functions. 8051 timer is a programmable timer in the 8051 microcontroller. The MC68230 timer developed by Motorola can provide a powerful timer architecture which can provide higher resolution than the Intel 8253.

5. How many bit architecture does MC68230 have?
a) 16
b) 24
c) 32
d) 40

View Answer

Answer: b [Reason:] The MC68230 timer have a 24-bit architecture which is splits into three 8-bit components because of the 8-bit bus in the MC68000 CPU.

6. How many bit bus does MC68230 have?
a) 2
b) 4
c) 8
d) 16

View Answer

Answer: c [Reason:] The MC68230 timer have a 24-bit architecture which is splits into three 8-bit components because of the 8-bit bus which is used for the communication with the host processor like MC68000 CPU which have an 8-bit architecture.

7. Which of the following is a timer processor?
a) Intel 8253
b) MC146818
c) MC68332
d) Intel 8259

View Answer

Answer: c [Reason:] Intel 8253 and 8259 are timers or counters which supports the processors. MC146818 is a real-time clock. MC68332 which is developed by Motorola is a 32 bit timer processor which can support MC68020.

8. What is the running frequency of MC68332?
a) 12 MHz
b) 14 MHz
c) 16 MHz
d) 18 MHz

View Answer

Answer: c [Reason:] The running frequency of the MC68332 is 16 MHz.

9. Which of the following is a real time clock?
a) MC146818
b) 8253
c) 8259
d) 8254

View Answer

Answer: a [Reason:] The 8253, 8254 and 8259 are timers or counters developed by Intel whereas MC146818 is a real-time clock.

Set 4

1. Which filesystem is used in the Windows 95?
a) FAT
b) HPFS
c) VFAT
d) NTFS

View Answer

Answer: c [Reason:] The VFAT is used in the Windows 95 and it also supports long file names.

2. What does HPFS stand for?
a) high performance file system
b) high periodic file system
c) high peripheral file system
d) horse power file system

View Answer

Answer: a [Reason:] The high performance file system is an alternative file system which possess 254 characters. It is used by the OS/2 and also write caching to disk technique that stores data temporarily and write it to the disk.

3. Which filing system is used by the Windows NT?
a) FAT
b) VFAT
c) HPFS
d) NTFS

View Answer

Answer: d [Reason:] The NT filing system or NTFS is used by the Windows NT, that is its own filing system which conforms to various security operations and allows system administrators to restrict access to files.

4. Which filesystem is used by the OS/2?
a) FAT
b) VFAT
c) HPFS
d) NTFS

View Answer

Answer: c [Reason:] The high performance file system is an alternative file system which possess 254 characters. It is used by the OS/2 and also write caching to disk technique that stores data temporarily and write it to the disk.

5. What do HAL stand for?
a) hardware abstraction layer
b) hardware address layer
c) hardware access layer
d) hardware address lead

View Answer

Answer: a [Reason:] The HAL is the hardware abstraction layer. This provides the portability across the multiprocessor and different platforms.

6. Which of the following can provide portability across different processor-based platforms?
a) File system
b) HAL
c) NTFS
d) FAT

View Answer

Answer: b [Reason:] The HAL or hardware abstraction layer is designed to provide portability across the different platform and different multiprocessor or single processor.

7. Which of the following defines the virtual hardware that the kernel uses?
a) HAL
b) NTFS
c) FAT
d) VFAT

View Answer

Answer: a [Reason:] The HAL or hardware abstraction layer defines a virtual hardware which the kernel uses when it needs to access the processor or hardware resources.

8. Which of the following provides a link between the user processes and threads and the hardware?
a) I/O driver
b) File system
c) Memory
d) LPC

View Answer

Answer: a [Reason:] The I/O driver is also a part of the kernel. These can provide a link between the threads and the processes and the hardware. The Windows NT driver is not compatible with the MS-DOS and Windows 3.1 drivers.

Set 5

1. From which of the following words does codecs is derived?
a) coder
b) decoder
c) coder-decoder
d) coder-encoder

View Answer

Answer: c [Reason:] The codec is derived coder-decoder and is coupled coupled to perform the coding. It can support both analogue to digital conversion and digital to analogue conversion.

2. Which codec is used in digital audio?
a) A-law
b) µ-law
c) linear
d) PCM

View Answer

Answer: c [Reason:] In the linear codec, the relationship between the analogue and digital values are linear. This method is commonly used in digital audio communication.

3. Which of the following have a same quantisation step throughout the range?
a) linear
b) PCM
c) DPCM
d) ADPCM

View Answer

Answer: a [Reason:] The quantisation step is same throughout the dynamic range in the linear codec and thus any increase in the analogue value increases the digital value, that is, the overall performance is linear.

4. Which is used in the telecommunication applications which has a limited bandwidth of 300 to 3100 HZ?
a) linear codec
b) logarithmic codec
c) PCM
d) DPCM

View Answer

Answer: b [Reason:] The logarithmic codec is frequently used in the telecommunication system which have a limited bandwidth of 300 to 3100 Hz. this can provide an 8-bit sample at 8 KHz,which are used in the telephones. The commonly used are A-law and µ-law.

5. Which codec is used in UK?
a) a-law
b) µ-law
c) linear codec
d) PCM

View Answer

Answer: a [Reason:] The a-law is a logarithmic codec which is commonly used in UK whereas µ-law is used in US.

6. What does PCM stand for?
a) pulse codec machine
b) pulse code modulation
c) peripheral code machine
d) peculiar code modulation

View Answer

Answer: b [Reason:] The linear codec is also known as pulse code modulation which is commonly used in the telecommunications industry.

7. Which of the following conversion is performed by using a lookup table?
a) DPCM
b) ADPCM
c) between DPCM and ADPCM
d) linear cdec and a-law

View Answer

Answer: d [Reason:] The conversion between a-law/µ-law and a linear digital signal or between µ-law and a-law is performed by a lookup table.

8. What does DPCM stand for?
a) differential pulse code modulation
b) data pulse code modulation
c) dynamic pulse code machine
d) dynamic pulse code modulation

View Answer

Answer: c [Reason:] The differential pulse code modulation is similar to pulse code modulation, but DPCM uses an encoded value which is the difference between the current and the previous sample.

9. Which of the following have a 16-bit digital dynamic range?
a) PCM
b) DPCM
c) linear codec
d) logarithmic codec

View Answer

Answer: b [Reason:] The differential pulse code modulation can improve the accuracy and resolution by having a 16-bit dynamic range. It works by the increasing dynamic range.

10. How many types of logarithmic codecs are used commonly?
a) 2
b) 3
c) 4
d) 5

View Answer

Answer: a [Reason:] There are two types of logarithmic codec which are commonly used. They are a-law which is used in UK and µ-law codec which is used in US.

11. What does ADPCM stand for?
a) address differential pulse code modulation
b) adaptive differential pulse code modulation
c) address dynamic pulse code machine
d) adaptive dynamic pulse code modulation

View Answer

Answer: b [Reason:] The adaptive differential pulse code modulation is used in telecommunications and is based on non-linear quantisation values.

12. Which of the following uses a non-linear quantisation value?
a) PCM
b) DPCM
c) ADPCM
d) linear codec

View Answer

Answer: c [Reason:] The adaptive differential pulse code modulation is based on non-linear quantisation values. In the ADPCM, instead of using all bit for encoding, only few bits are used for encoding which makes it non linear.

13. Which of the following works by increasing the dynamic range?
a) logarithmic codec
b) linear codec
c) DPCM
d) PCM

View Answer

Answer: c [Reason:] The differential pulse code modulation can improve the accuracy and resolution by having a 16-bit dynamic range. It works by the increasing dynamic range.

14. Which device can make the PWM operation easier?
a) timer
b) software
c) hardware
d) transistor

View Answer

Answer: a [Reason:] The timer can be used for making up the PWM waveform far more easier and faster and it will free the processor to do other things without affecting the timing.