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## Computer Networks MCQ Set 1

1. The product of 1101 & 1011 is
a) 10001111
b) 10101010
c) 11110000
d) 11001100

Answer: a [Reason:] The above operation is performed using binary multiplication.

2. We make use of ______ circuits to implement multiplication.
a) Flip flops
b) Combinatorial
d) None of the mentioned

3. The multiplier is stored in ______
a) PC Register
b) Shift register
c) Cache
d) None of the mentioned

Answer: b [Reason:] The value is stored in a shift register, so that each bit can be accessed separately.

4. The ______ is used to co-ordinate the operation of the multiplier.
a) Controller
b) Coordinator
c) Control sequencer
d) None of the mentioned

Answer: c [Reason:] This performs the required sequencing of the various parts of the circuit.

5. The multiplicand and the control signals are passed through to the n-bit adder via _____
a) MUX
b) DEMUX
c) Encoder
d) Decoder

6. The product of -13 & 11 is
a) 1100110011
b) 1101110001
c) 1010101010
d) 1111111000

7. The method used to reduce the maximum number of summands by half is _______
a) Fast multiplication
b) Bit-pair recording
c) Quick multiplication
d) None of the mentioned

Answer: b [Reason:] It reduces the number of summands by concatenating them.

8. The bits 1 & 1 are recorded as _______ in bit-pair recording.
a) -1
b) 0
c) +1
d) both -1 and 0

Answer: d [Reason:] Its ‘-1’ when the previous bit is 0 and ‘0’ when the previous bit is 1.

9. The multiplier -6(11010) is recorded as,
a) 0-1-2
b) 0-1+1-10
c) -2-10
d) None of the mentioned

10. CSA stands for
c) Computer Service Architecture
d) None of the mentioned

Answer: a [Reason:] The CSA is used to speed up the addition of multiplicands.

## Computer Networks MCQ Set 2

1. The _____ circuit enables the generation of the ASCII code when the key is pressed.
a) Generator
b) Debouncing
c) Encoder
d) Logger

Answer: c [Reason:] The signal generated upon the pressing of a button is encoded by the encoder circuit into the corresponding ASCII value.

2. To overcome multiple signals being generated upon a single press of the button, we make use of ______
a) Generator circuit
b) Debouncing circuit
c) Multiplexer
d) XOR circuit

Answer: b [Reason:] When the button is pressed,the contact surfaces bounce and hence it might lead to generation of multiple signals.In order to overcome this we use Debouncing circuits.

3. The best mode of conncetion between devices which need to send or recieve large amounts of data over a short distance is _____
a) BUS
b) Serial port
c) Parallel port
d) Isochronous port

Answer: c [Reason:] The parallel port transfers around 8 to 16 bits of data simultaneously over the lines, hence increasing transfer rates.

4. The output of the encoder circuit is/are ______
a) ASCII code
b) ASCII code and the valid signal
c) Encoded signal
d) None of the mentioned

Answer: b [Reason:] The encoder outputs the ASCII value along with the valid signal which indicates that a key was pressed.

5. The disadvantage of using parallel mode of communication is ______
a) It is costly
b) Leads to erroneous data transfer
c) Security of data
d) All of the mentioned

Answer: a [Reason:] The parallel mode of data transfer is costly as it involves data being sent over parallel lines.

6. In a 32 bit processor, the A0 bit of the address line is connected to _____ of the parallel port interface.
a) Valid bit
b) Idle bit
c) Interrupt enable bit
d) Status or data register

7. The Status flag circuit is implemented using _____
a) RS flip flop
b) D flip flop
c) JK flip flop
d) Xor circuit

Answer: b [Reason:] The circuit is implemented using the edge triggered D flip flop, that is triggered on the rising edge of the valid signal.

8. In the output interface of the parallel port, along with the valid signal ______ is also sent.
a) Data
b) Idle signal
c) Interrupt
d) Acknowledge signal

Answer: b [Reason:] The idle signal is used to check if the device is idle and ready to receive data.

9. DDR stands for __________
a) Data Direction Register
b) Data Decoding Register
c) Data Decoding Rate
d) None of the mentioned

Answer: a [Reason:] This register is used to control the flow of data from the DATAOUT register.

10. In a general 8-bit parallel interface, the INTR line is connected to _______
a) Status and Control unit
b) DDR
c) Register select
d) None of the mentioned

## Computer Networks MCQ Set 3

1. The PCI follows a set of standards primarily used in _____ PC’s.
a) Intel
b) Motorola
c) IBM
d) SUN

Answer: c [Reason:] The PCI BUS has a closer resemblance to IBM architecture.

2. The ______ is the BUS used in Macintosh PC’s.
a) NuBUS
b) EISA
c) PCI
d) None of the mentioned

Answer: a [Reason:] The NuBUS is an extension of the processor BUS in Macintosh PC’s.

3. The key feature of the PCI BUS is
a) Low cost connectivity
b) Plug and Play capability
c) Expansion of Bandwidth
d) None of the mentioned

Answer: b [Reason:] The PCI BUS was the first to introduce plug and play interface for I/O devices.

4. PCI stands for _______
a) Peripheral Component Interconnect
b) Peripheral Computer Internet
c) Processor Computer Interconnect
d) Processor Cable Interconnect

Answer: a [Reason:] The PCI BUS is used as an extension for the processor BUS.

5. The PCI BUS supports _____ address space/s.
a) I/O
b) Memory
c) Configuration
d) All of the mentioned

Answer: d [Reason:] The PCI BUS is mainly built to provide a wide range of connectivity for devices.

6. ______ address space gives the PCI its plug and play capability.
a) Configuration
b) I/O
c) Memory
d) All of the mentioned

Answer: a [Reason:] The coniguration address space is used to store the details of the connected device.

7. _____ provides a seperate physical connection to the memory.
a) PCI BUS
b) PCI interface
c) PCI bridge
d) Switch circuit

Answer: c [Reason:] The PCI bridge is circuit that acts as a bridge between the BUS and the memory.

8. When transfering data over the PCI BUS, the master as to hold the address till the completion of transfer to the slave.
a) True
b) False

Answer: b [Reason:] The address is stored by the slave in a buffer and hence it is not required by the master to hold it.

9. The master is also called as _____ in PCI terminology.
a) Initiator
b) Commander
c) Chief
d) Starter

Answer: a [Reason:] The Master is also called as initiator in PCI terminology as it is the one that initiates a data transfer.

10. Signals whose names end in ____ are asserted in the low voltage state.
a) \$
b) #
c) *
d) !

## Computer Networks MCQ Set 4

1. The key factor/s in commercial success of a computer is/are ________
a) Performance
b) Cost
c) Speed
d) Both Performance and Cost

Answer: d [Reason:] The performance and cost of the computer system is key decider in the commercial success of the system.

2. The main objective of the computer system is
a) To provide optimal power operation
b) To provide best performance at low cost
c) To provide speedy operation at low power consumption
d) All of the mentioned

Answer: b [Reason:] An optimal system provides best performance at low costs.

3. A common measure of performance is
a) Price/performance ratio
b) Performance/price ratio
c) Operation/price ratio
d) None of the mentioned

Answer: a [Reason:] If this measure is less than one then the system is optimal.

4. The performance depends on
a) The speed of execution only
b) The speed of fetch and execution
c) The speed of fetch only
d) The hardware of the system only

Answer: b [Reason:] The performance of a system is decided by how quick an instruction is brought into the system and executed.

5. The main purpose of having memory hierarchy is to
a) Reduce access time
b) Provide large capacity
c) Reduce propagation time
d) Reduce access time & Provide large capacity

Answer: d [Reason:] By using the memory Hierarchy, we can increase the performance of the system.

6. The memory transfers between two variable speed devices is always done at the speed of the faster device.
a) True
b) False

7. An effective to introduce parallelism in memory access is by _______
a) Memory interleaving
b) TLB
c) Pages
d) Frames

Answer: a [Reason:] Interleaving divides the memory into modules.

8. The performance of the system is greatly influenced by increasing the level 1 cache.
a) True
b) False

Answer: a [Reason:] This is so because the L1 cache is onboard the processor.

9. Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an average
of 3 steps and B can execute with an average of 5 steps.For the execution of the same instruction which processor is faster
a) A
b) B
C) Both take the same time
d) Insufficient information

10.If the instruction Add R1, R2, R3 is executed in a system which is pipelined, then the value of S is (Where S is term of the Basic performance equation)
a) 3
b) ~2
C) ~1
d) 6

Answer: c [Reason:] Pipelining is a process of fetching an instruction during the execution of other instruction.

## Computer Networks MCQ Set 5

1. During the execution of the instructions, a copy of the instructions is placed in the ______
a) Register
b) RAM
c) System heap
d) Cache

2. Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction which processor is faster ?
a) A
b) B
C) Both take the same time
d) Insuffient information

Answer: a [Reason:] The performance of a system can be found out using the Basic performance formula.

3. A processor performing fetch or decoding of different instruction during the execution of another instruction is called ______
a) Super-scaling
b) Pipe-lining
c) Parallel Computation
d) None of the mentioned

Answer: b [Reason:] Pipe-lining is the process of improving the performance of the system by processing different instructions at the same time, with only one instruction performing one specific operation.

4. For a given FINITE number of instructions to be executed, which architecture of the processor provides for a faster execution ?
a) ISA
b) ANSA
c) Super-scalar
d) All of the mentioned

Answer: c [Reason:] In super-scalar architecture, the instructions are set in groups and they’re decoded and executed together reducing the amount of time required to process them.

5. The clock rate of the processor can be improved by _________
a) Improving the IC technology of the logic circuits
b) Reducing the amount of processing done in one step
c) By using overclocking method
d) All of the mentioned

Answer: d [Reason:] The clock rate(frequency of the processor) is the hardware dependent quantity it is fixed for a given processor.

6. An optimizing Compiler does _________
a) Better compilation of the given piece of code
b) Takes advantage of the type of processor and reduces its process time
c) Does better memory managament
d) none of the mentioned

Answer: b [Reason:] An optimizing compiler is a compiler designed for the specific purpose of increasing the operation speed of the processor by reducing the time taken to compile the program instructions.

7. The ultimate goal of a compiler is to ________
a) Reduce the clock cycles for a programming task
b) Reduce the size of the object code
c) Be versatile
d) Be able to detect even the smallest of errors

8. SPEC stands for _______
a) Standard Performance Evaluation Code
b) System Processing Enhancing Code
c) System Performance Evaluation Corporation
d) Standard Processing Enhancement Corporation

Answer: c [Reason:] SPEC is a corporation started to standardize the evaluation method of a systems performance.

9. As of 2000, the reference system to find the performance of a system is _____
a) Ultra SPARC 10
b) SUN SPARC
c) SUN II
d) None of the mentioned

Answer: a [Reason:] In SPEC system of measuring a systems performance, a system is used as a reference against which other systems are compared and performance is determined.

10. When Performing a looping operation, the instruction gets stored in the ______
a) Registers
b) Cache
c) System Heap
d) System stack

Answer: b [Reason:] When a looping or branching operation is carried out the offset value is stored in the cache along with the data.

11. The average number of steps taken to execute the set of instructions can be made to be less than one by following _______
a) ISA
b) Pipe-lining
c) Super-scaling
d) Sequential

Answer: c [Reason:] The number of steps required to execute a given set of instructions is sufficiently reduced by using super-scaling. In this method a set of instructions are grouped together and are processed.

12. If a processor clock is rated as 1250 million cycles per second, then its clock period is ________
a) 1.9 * 10-10 sec
b) 1.6 * 10-9 sec
c) 1.25 * 10-10 sec
d) 8 * 10-10 sec

13. If the instruction, Add R1, R2, R3 is executed in a system which is pipe-lined, then the value of S is (Where S is term of the Basic performance equation)
a) 3
b) ~2
C) ~1
d) 6

Answer: c [Reason:] S is the number of steps required to execute the instructions.

14. CISC stands for _______
a) Complete Instruction Sequential Compilation
b) Computer Integrated Sequential Compiler
c) Complex Instruction Set Computer
d) Complex Instruction Sequential Compilation